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    CIRCUIT FOR READING OUT MEMORY CELL PROVIDED WITH FERROELECTRIC CAPACITOR
    2.
    发明专利
    CIRCUIT FOR READING OUT MEMORY CELL PROVIDED WITH FERROELECTRIC CAPACITOR 失效

    公开(公告)号：JP2001351374A

    公开(公告)日：2001-12-21

    申请号：JP2001121421

    申请日：2001-04-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ

    IPC: G11C11/22

    Abstract: PROBLEM TO BE SOLVED: To constitute a circuit so that the ratio of bit line capacitance to the capacitance of a ferroelectric capacitor can be selected over further wider range, in a circuit for reading out a memory cell provided with a ferroelectric capacitor. SOLUTION: This circuit is provided with a bit line BL connected to a memory cell FSPZ and a differential amplifier D. An input side DE1 of a first differential amplifier is connected to the bit line BL, and a reference signal VBSOLL is supplied to a second differential amplifier DE2. The device is also provided with a first driver circuit TR1 provided with a driver input side TRE1 and a first driver output side TRA1. A differential amplifier output side DA is connected to the first driver input side TRE1, and the first driver output side TRA1 is connected to the bit line BL, and a potential of the bit line BL is controlled according to a potential of the reference signal VBSOLL.

    INTEGRATED MEMORY
    3.
    发明专利
    INTEGRATED MEMORY 失效

    公开(公告)号：JP2001291386A

    公开(公告)日：2001-10-19

    申请号：JP2001047191

    申请日：2001-02-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRAUN GEORG ,  HONIGSCHMID HEINZ

    IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105

    Abstract: PROBLEM TO BE SOLVED: To suppress occurrence of an error more than a publicly-known memory by providing an integrated memory. SOLUTION: This memory is provided with a driver unit, and a column selection line is connected to a plate type line segment through this driver unit, The driver unit forms a potential of a prescribed value for respective operation state of memories depending on a potential of a belonging column selection line and a word address of a connected plate type line segment.

    INTEGRATED MEMORY AND OPERATION OF MEMORY
    4.
    发明专利
    INTEGRATED MEMORY AND OPERATION OF MEMORY 失效

    公开(公告)号：JP2000353398A

    公开(公告)日：2000-12-19

    申请号：JP2000126387

    申请日：2000-04-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG

    IPC: G01R31/28 ,  G11C11/22 ,  G11C11/401 ,  G11C11/406 ,  G11C14/00 ,  G11C29/34 ,  G11C29/00

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated memory in which simultaneous write-in of the same logic information is easily performed in plural memory cells. SOLUTION: An integrated memory has bit lines BLi, word lines WLk, and memory cells MC arranged at intersections of plate electrode lines PLi. In a first operation mode, a plate electrode line PLi is left at a plate electrode potential VPL of a fixed period of write-in access. In a second operation mode, the bit line is left at a plate electrode potential, on the other hand, a plate electrode line PLi takes the prescribed potential VF other than the plate electrode potential VPL.

    MEMORY DEVICE HAVING PLURAL MEMORY CELLS
    7.
    发明专利
    MEMORY DEVICE HAVING PLURAL MEMORY CELLS 失效

    公开(公告)号：JP2000156091A

    公开(公告)日：2000-06-06

    申请号：JP32163899

    申请日：1999-11-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG

    IPC: G11C14/00 ,  G11C11/22

    Abstract: PROBLEM TO BE SOLVED: To reduce remarkably a time for reading out by connecting respectively one short circuit element to one side bit line of two pairs of bit line, applying a reference signal to a sense amplifier through a first pair of bit line, simultaneously, applying a read-out signal to the sense amplifier through a second pair of bit line. SOLUTION: In a short circuit element SG, being not adjacent bit lines, but every other bit lines are connected mutually. This way is indicated by a bit line BL , BL or bBL , bBL , further, in this case, two control lines INIT , INIT are not used for pre-charge, but used for short-circuiting two bit lines BL , BL or bBL , bBL . Active memory cells L and a reference cell R are arranged comparatively densely in the same block as a memory cell field by arranging utilized pairs of bit line in parallel.

    DRAM WITH BIT LINES IN TWO METALLISED SHEETS
    8.
    发明申请
    DRAM WITH BIT LINES IN TWO METALLISED SHEETS 审中-公开
    在两个金属与DRAM位线

    公开(公告)号：WO0127974A3

    公开(公告)日：2001-10-18

    申请号：PCT/EP0009739

    申请日：2000-10-05

    Applicant: INFINEON TECHNOLOGIES AG ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG

    Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG

    IPC: G11C5/10 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10885 ,  G11C5/10 ,  H01L27/10811 ,  H01L27/10814

    Abstract: The invention relates to a memory device comprising numerous memory cells, each cell comprising at least one selection transistor and one stacked capacitor and being driven via word (3) and bit lines (14, 16). Said memory device is characterised in that the bit lines (14, 16) are led through two metallised sheets and in that the stacked capacitors (7, 8, 9) of the memory cells are located between these metallised sheets.

    Abstract translation: 根据本发明，提供了一种具有多个存储器单元的存储器装置的每一个包括至少一个选择晶体管和一个叠置电容器和经由字（3） - 和位线（14，16）是可控的。 根据本发明的存储系统的特征在于：（14，16）在两个金属化被引导所述位线和所述层叠电容器（7，8，9）的金属化平面之间的存储器单元的布置。

    9.
    发明专利
    未知

    公开(公告)号：DE10146491B4

    公开(公告)日：2006-04-13

    申请号：DE10146491

    申请日：2001-09-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KANDOLF HELMUT ,  BRAUN GEORG

    IPC: H04L25/06 ,  H03K19/00 ,  H03K19/0175 ,  H04B3/04 ,  H04L12/40

    Abstract: An electronic circuit has a driver circuit to drive a signal onto a signal line. The driver circuit contains a first switching device with a first forward resistance between a first supply voltage terminal and the signal line, and a second switching device with a second forward resistance between a second supply voltage terminal and the signal line. A control circuit is provided to generate a first and a second control signal to control the first and second switching devices in a first operating mode such that, depending on the signal which is to be driven, either the first switching device or the second switching device is through-connected. In a second operating mode, the first switching device and the second switching device are essentially through-connected with the aid of the first and second control signals so that the first and second forward resistances together form a terminating resistance.

    10.
    发明专利
    未知

    公开(公告)号：DE10121241B4

    公开(公告)日：2005-07-07

    申请号：DE10121241

    申请日：2001-04-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MUFF SIMON ,  GALL MARTIN ,  SCHAEFER ANDRE ,  BRAUN GEORG

    IPC: H01L23/34 ,  H01L23/495 ,  H01L23/50 ,  H01L23/66

    Abstract: An integrated circuit which is integrated in a housing having connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit, each connecting pin connected by an associated wiring line to a contact pad of the circuit integrated in the housing, to exchange signals between the external circuit and the integrated circuit, where to minimize the line lengths of the associated wiring lines, the connecting pins to be connected to signal lines for high-frequency signals are fitted centrally to the housing.

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