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公开(公告)号：AT285599T
公开(公告)日：2005-01-15
申请号：AT02732380
申请日：2002-04-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SEDLAK HOLGER , KNIFFLER OLIVER , WEDER UWE , GUO SHUWEI
Abstract: A frequency regulating circuit for the current-consumption-dependent clock supply of a circuit configuration includes a current measuring device for measuring the instantaneous current consumption of the circuit configuration, a controllable clock supply circuit, which can be connected to a clock input of the circuit configuration, and a control device for driving the clock supply circuit based upon the measured current consumption, an increase in the current consumption of the circuit configuration effecting a reduction in the clock frequency at the output of the clock supply circuit. Such a circuit ensures that a maximum permissible current consumption is not exceeded, but, at the same time, makes possible a maximum power of the circuit by a maximum clock frequency.
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公开(公告)号：DE10201450B4
公开(公告)日：2004-09-02
申请号：DE10201450
申请日：2002-01-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KLUG FRANZ , KNIFFLER OLIVER , GAMMEL BERNDT
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公开(公告)号：DE10121821A1
公开(公告)日：2002-11-14
申请号：DE10121821
申请日：2001-05-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SEDLAK HOLGER , KNIFFLER OLIVER , WEDER UWE , GUO SHUWEI
Abstract: The invention relates to a frequency control circuit for supplying clock-pulses, depending on the current consumption, to a circuit arrangement. Said frequency control circuit comprises a current measuring device (2) for measuring the instantaneous current consumption of the circuit arrangement (1), a controllable clock-pulse supply circuit (4) which can be connected to a clock-pulse input of the circuit arrangement (1), and a control device (3) for controlling the clock-pulse supply circuit (4) on the basis of the measured current consumption. An increase in the current consumption of the circuit arrangement causes a reduction in the clock-pulse frequency at the output (6) of the clock-pulse supply circuit (4). Said circuit ensures that a maximum acceptable current consumption is not exceeded, at the same time enabling maximum power of the circuit due to a maximum clock-pulse frequency.
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14.发明专利
公开(公告)号：DE102005022107B9
公开(公告)日：2016-04-07
申请号：DE102005022107
申请日：2005-05-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GÖTTFERT RAINER , GAMMEL BERNDT , KNIFFLER OLIVER
Abstract: In einer Vorrichtung zum Bestimmen einer Position eines Bitfehlers in einer Bitfolge wird eine Kontrollmatrix (H) verwendet, die eine vordefinierte Zeilenanzahl und eine vordefinierte Spaltenanzahl aufweist. Die Kontrollmatrix (H) umfasst eine Mehrzahl von quadratischen Teilmatrizen (A0, ..., A3), die eine Teilmatrixzeilenanzahl und eine Teilmatrixspaltenanzahl haben, die der vordefinierten Zeilenanzahl oder der vordefinierten Spaltenanzahl der Kontrollmatrix (A) entspricht. Die Vorrichtung zum Bestimmen umfasst dann eine Einrichtung (102) zum Empfangen einer Bitfolge sowie eine Einrichtung (104) zum Ermitteln eines Syndroms unter Verwendung der Kontrollmatrix (H) und der empfangenen Bitfolge (y). Ferner umfasst die Vorrichtung eine Einrichtung (106) zum Feststellen einer Position (r) eines Bitfehlers in der empfangenen Bitfolge (y), wobei die Einrichtung zum Feststellen (106) ausgebildet ist, um in dem Syndrom ein Syndrombit und eine Syndrombitgruppe zu identifizieren und wobei die Einrichtung (106) zum Feststellen ferner ausgebildet ist, um unter Verwendung einer Information über eine Position des Syndrombits oder der Syndrombitgruppe in dem Syndrom, eine Information über eine Beziehung zwischen dem Syndrombit und der Syndrombitgruppe und einer Teilmatrixzeilenanzahl oder einer Teilmatrixspaltenanzahl einer Teilmatrix die Position des Bitfehlers in der empfangenen Bitfolge zu bestimmen.
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公开(公告)号：AT367609T
公开(公告)日：2007-08-15
申请号：AT00965852
申请日：2000-09-20
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SEDLAK HOLGER , KNIFFLER OLIVER , GAERTNER WOLFGANG
IPC: G06F13/362
Abstract: A method of operating a processor bus, with which a central unit (processor) makes accesses to various peripheral units, is described. The processor bus has the ability to change the order of the accesses as a function of the operating state of the peripheral units, and the peripheral units can either reject or delay the access.
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Patent Agency Ranking
公开(公告)号：DE102004025418A1
公开(公告)日：2005-12-22
申请号：DE102004025418
申请日：2004-05-24
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KLUG FRANZ , KNIFFLER OLIVER , SONNEKALB STEFFEN , WENZEL ANDREAS
Abstract: A controller has a receiver for receiving an instruction, the instruction being an executable instruction or a wildcard instruction. A decoder is formed to output a control signal corresponding to the executable instruction responsive to an executable instruction, and to output a switch signal responsive to a received wildcard instruction. Additionally, the controller has a provider for providing a predetermined substitute control signal outputting the predetermined substitute control signal depending on the switch signal.
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公开(公告)号：DE10217291B4
公开(公告)日：2005-09-29
申请号：DE10217291
申请日：2002-04-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KLUG FRANZ , KNIFFLER OLIVER
IPC: G06K19/073 , G06F1/26 , G06F12/14 , G07C15/00
Abstract: Data processing device comprises a data processing module (10) that can be operated in two modes. In the first mode it is operated with normal power use, while in the second mode it operates with reduced or zero power use. A signaler (12) is provided for signaling that the data processing device can be switched into its second mode. Random variation of the operation mode, provided by use of a random number generator in conjunction with the device controller, ensures that the device is protected against differential power analysis. The invention also relates to a corresponding method for operating a data processing device.
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公开(公告)号：AT297569T
公开(公告)日：2005-06-15
申请号：AT02714018
申请日：2002-02-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KNIFFLER OLIVER , SEDLAK HOLGER
IPC: G06F13/42
Abstract: A data bus configuration has a data bus which can be operated in a multiplex mode and to which at least one control station and a reception station are connected. The data bus configuration further has a control bus via which the control station can allocate a logical channel to the reception station.
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公开(公告)号：DE10121821B4
公开(公告)日：2004-04-08
申请号：DE10121821
申请日：2001-05-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SEDLAK HOLGER , KNIFFLER OLIVER , WEDER UWE , GUO SHUWEI
Abstract: A frequency regulating circuit for the current-consumption-dependent clock supply of a circuit configuration includes a current measuring device for measuring the instantaneous current consumption of the circuit configuration, a controllable clock supply circuit, which can be connected to a clock input of the circuit configuration, and a control device for driving the clock supply circuit based upon the measured current consumption, an increase in the current consumption of the circuit configuration effecting a reduction in the clock frequency at the output of the clock supply circuit. Such a circuit ensures that a maximum permissible current consumption is not exceeded, but, at the same time, makes possible a maximum power of the circuit by a maximum clock frequency.
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公开(公告)号：DE50003679D1
公开(公告)日：2003-10-16
申请号：DE50003679
申请日：2000-12-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GAMMEL BERNDT , KNIFFLER OLIVER , SEDLAK HOLGER
Abstract: A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key register. A memory is provided with a further encryption unit whose gate is connected between the register and the gate of the first encryption unit. As a result, the transferred information item is available in encrypted form at any point on the bus.
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