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    INTEGRATED CIRCUIT WITH LOW ENERGY CONSUMPTION IN A POWER SAVING MODE
    2.
    发明申请
    INTEGRATED CIRCUIT WITH LOW ENERGY CONSUMPTION IN A POWER SAVING MODE 审中-公开
    随着节能低能耗集成电路

    公开(公告)号：WO02082248A3

    公开(公告)日：2003-07-31

    申请号：PCT/DE0200821

    申请日：2002-03-07

    Applicant: INFINEON TECHNOLOGIES AG ,  WEDER UWE ,  SEDLAK HOLGER

    Inventor： WEDER UWE ,  SEDLAK HOLGER

    IPC: G06F1/32

    CPC classification number: G06F1/3243 ,  G06F1/32 ,  Y02D10/152

    Abstract: The invention relates to an integrated circuit comprising at least one voltage regulator, which is connected between a supply potential terminal and a reference potential terminal. The integrated circuit also has at least one useful circuit, which contains a memory and/or logic unit, whose supply potential input is coupled to the output of the voltage regulator. According to the invention, the voltage regulator can be switched off by a first switching device in a power saving mode. The supply potential input of the useful circuit is then connected to the supply potential terminal via a diode circuit.

    Abstract translation: 本发明提出了具有电源电位端子与张力调节器相互连接的基准电位端子之间的至少一个集成电路，其进一步包括至少一个存储器和/或逻辑包括利用电路中，源极电势输入端耦合到所述电压调节器的输出。 根据本发明，通过第一开关装置在电压调节器的功率节省模式关闭。 利用电路的源极电位的输入，然后通过一个二极管电路到电源电位连接而连接。

    CLOCK GENERATOR, PARTICULARLY FOR USB DEVICES
    3.
    发明申请
    CLOCK GENERATOR, PARTICULARLY FOR USB DEVICES 审中-公开
    时钟发生器，特别是USB设备

    公开(公告)号：WO0217047A3

    公开(公告)日：2003-01-09

    申请号：PCT/DE0103187

    申请日：2001-08-21

    Applicant: INFINEON TECHNOLOGIES AG ,  BRUHNKE MICHAEL ,  PREIS VIKTOR ,  WEDER UWE

    Inventor： BRUHNKE MICHAEL ,  PREIS VIKTOR ,  WEDER UWE

    IPC: G06F1/12 ,  G06F1/04 ,  H03L7/00 ,  H04L7/02

    CPC classification number: H03L7/00 ,  G06F1/04

    Abstract: An accuracy in the data transfer rate of 0.25 % is required according to USB specifications. In order to generate a clock signal, which renders this accuracy possible, the invention enlists the use of a clock generator unit that operates without quartz. The inventive clock generator unit comprises an internal clock generator (11), a pulse counter (17), which is connected to the internal clock generator (11), a pulse number memory (18), and a pulse filter (14). The pulse counter counts the number of the internally generated clock pulses between two pulses of the synchronization signal (16), which are transmitted according to the USB specification. The difference between the determined pulse number and a specified pulse number is evaluated and is used for controlling the pulse filter (14) that suppresses pulses, thereby resulting in the generation of a stabilized clock signal (13).

    Abstract translation: 根据USB规范要求在0.25％的数据传输速率的精度。 为了产生一个时钟信号，该信号能够使该精度，时钟发生器单元根据不需要石英本发明使用。 根据本发明的时钟发生器单元包括一个内部时钟发生器（11），其与所述内部时钟发生器（11）连接的脉冲计数器（17），脉冲数存储器（18）和一个脉冲滤波器（14）。 脉冲计数器计数所述同步信号（16），其根据USB规范发送的两个脉冲之间内部生成的时钟脉冲的数目。 脉冲的检测的数量和脉冲的期望数量之间的差被评估并用于控制脉冲抑制过滤器（14）的脉冲。 这就产生了一个稳定的时钟信号（13）。

    5.
    发明专利
    未知

    公开(公告)号：AT418755T

    公开(公告)日：2009-01-15

    申请号：AT01969248

    申请日：2001-08-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRUHNKE MICHAEL ,  PREIS VIKTOR ,  WEDER UWE

    IPC: G06F1/04 ,  G06F1/12 ,  H03L7/00 ,  H04L7/02

    Abstract: In accordance with the USB specifications, an accuracy of 0.25% is required for the data transmission rate. To generate a clock signal that allows this accuracy, the invention uses a clock generator unit that does not require a crystal. The clock generator unit includes an internal clock generator, a pulse counter that is connected to the internal clock generator, a pulse number memory, and a pulse filter. The pulse counter counts the number of internally generated clock pulses between two pulses of the synchronization signal, which are transmitted in accordance with the USB specification. The difference between the ascertained pulse number and a nominal pulse number is evaluated and is used for controlling the pulse-suppressing pulse filter. This results in a stabilized clock signal.

    7.
    发明专利
    未知

    公开(公告)号：AT285599T

    公开(公告)日：2005-01-15

    申请号：AT02732380

    申请日：2002-04-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEDLAK HOLGER ,  KNIFFLER OLIVER ,  WEDER UWE ,  GUO SHUWEI

    IPC: G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  H03L7/00

    Abstract: A frequency regulating circuit for the current-consumption-dependent clock supply of a circuit configuration includes a current measuring device for measuring the instantaneous current consumption of the circuit configuration, a controllable clock supply circuit, which can be connected to a clock input of the circuit configuration, and a control device for driving the clock supply circuit based upon the measured current consumption, an increase in the current consumption of the circuit configuration effecting a reduction in the clock frequency at the output of the clock supply circuit. Such a circuit ensures that a maximum permissible current consumption is not exceeded, but, at the same time, makes possible a maximum power of the circuit by a maximum clock frequency.

    9.
    发明专利
    未知

    公开(公告)号：BR0115919A

    公开(公告)日：2003-09-16

    申请号：BR0115919

    申请日：2001-11-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WEDER UWE

    IPC: G06F1/26 ,  G05F1/56 ,  G05F1/565 ,  G06K7/00 ,  G06K19/07 ,  G06K19/073 ,  H02M1/14 ,  H02M3/156 ,  H02P9/30

    Abstract: The circuit contains a series regulator with an FET. A capacitor and a further FET, which is provided as a transfer gate and is driven by the POR signal, are connected in series between the source terminal, to which the external supply voltage is applied, and the gate connection. When the external voltage is applied, the FET opens, with the transfer gate switched on, corresponding to the charging of the capacitor which now takes place. Because this charging process takes a certain amount of time, overshoots in the internal voltage are prevented.

    10.
    发明专利
    未知

    公开(公告)号：BR0113471A

    公开(公告)日：2003-07-15

    申请号：BR0113471

    申请日：2001-08-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRUHNKE MICHAEL ,  PREIS VIKTOR ,  WEDER UWE

    IPC: G06F1/12 ,  G06F1/04 ,  H03L7/00 ,  H04L7/02 ,  G06F1/00

    Abstract: In accordance with the USB specifications, an accuracy of 0.25% is required for the data transmission rate. To generate a clock signal that allows this accuracy, the invention uses a clock generator unit that does not require a crystal. The clock generator unit includes an internal clock generator, a pulse counter that is connected to the internal clock generator, a pulse number memory, and a pulse filter. The pulse counter counts the number of internally generated clock pulses between two pulses of the synchronization signal, which are transmitted in accordance with the USB specification. The difference between the ascertained pulse number and a nominal pulse number is evaluated and is used for controlling the pulse-suppressing pulse filter. This results in a stabilized clock signal.

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