公开(公告)号：DE10315050A1

公开(公告)日：2003-11-27

申请号：DE10315050

申请日：2003-04-02

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD ,  HANSON DAVID

IPC: H03K19/0185 ,  H03L5/00

Abstract: A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

公开(公告)号：DE10314615A1

公开(公告)日：2003-10-23

申请号：DE10314615

申请日：2003-04-01

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: H03F3/04 ,  H03K19/0175 ,  H03K19/094

Abstract: A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.

公开(公告)号：DE69911102D1

公开(公告)日：2003-10-16

申请号：DE69911102

申请日：1999-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD

IPC: G11C11/401 ,  G11C5/06 ,  G11C7/10 ,  G11C8/14 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00 ,  G11C11/408 ,  G11C11/409

Abstract: A memory circuit having a stitched architecture wherein word lines of the memory circuit comprise a low resistance conductor stitched to a gate conductor portion having a higher resistance than the low resistance conductor. The memory circuit includes an array of memory cells having thereon bit lines disposed generally along a first direction and the word lines disposed generally along a second direction substantially orthogonal to the first direction. The memory circuit also includes an array sense amplifier region disposed adjacent the array of memory cells generally along the first direction. The array sense amplifier region has therein a plurality of array sense amplifiers coupled to the bit lines. The memory circuit further includes a stitch region containing contacts for stitching the low resistance conductor with the gate conductor. The stitch region is disposed adjacent the array of memory cells generally along the second direction. There is further included a set of local data lines disposed generally along the second direction and coupled to the plurality of array sense amplifiers. There is also included a set of master data switches coupled to the set of local data lines. The master data switch is disposed in a contact-free portion of the stitch region that is adjacent to the array sense amplifier region generally along the second direction. The memory circuit further includes a set of master data lines disposed generally along the first direction and a set of master line-to-switch connectors disposed generally along the second direction for coupling the set of master data lines to the set of master data switches, wherein the set of bit lines, the set of master data lines, the low resistance conductors of the word lines, the set of local data lines, and the set of master line-to-switch connectors are formed from at least four different conductor layers of the memory circuit.

公开(公告)号：DE10243469A1

公开(公告)日：2003-05-08

申请号：DE10243469

申请日：2002-09-19

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KIRLHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C29/00 ,  G06F11/16 ,  H01L23/525

Abstract: Multiple conductive paths are provided in a circuit portion between a circuit element and a logic block, enabling repairing of defects in the conductive line coupling the circuit element and logic blocks without the use of fusing.

公开(公告)号：DE10054521A1

公开(公告)日：2002-02-14

申请号：DE10054521

申请日：2000-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  MUELLER GERHARD

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/10 ,  G11C7/00 ,  G11C8/00

Abstract: A method for reading data from a memory arrangement (15-18) having several memory units (11-14), each of the latter having memory cells equipped with word- and bit-lines; the memory units have a word-line decoder (2) and a bit-line decoder (3). An address decoder (21) is connected to the word-line decoders (2) and to the bit-line decoders (3). Data is read out from the memory cells alternately from different memory units (11-14).

公开(公告)号：DE50113766D1

公开(公告)日：2008-04-30

申请号：DE50113766

申请日：2001-12-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  MUELLER GERHARD

IPC: G11C11/22 ,  G11C8/02 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115

Abstract: A memory device is configured to guarantee a high degree of flexibility and a compact construction. To this end, the existing plate line device of the memory device which functions on the basis of a hysteresis process is configured to detect the state of a memory capacitor and hence, the information that is stored.

公开(公告)号：DE60028099T2

公开(公告)日：2006-12-07

申请号：DE60028099

申请日：2000-01-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: G11C7/10 ,  G11C11/41 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/417 ,  H03K19/017

Abstract: A high frequency driver circuit is described. The driver produces increased current flow at its output to decrease charging time, thereby enabling higher frequency operations. Increased current flow is achieved by providing an active control signal that increases the magnitude of the overdrive voltage applied to a driver transistor.

公开(公告)号：DE69832566T2

公开(公告)日：2006-08-10

申请号：DE69832566

申请日：1998-09-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  HOENIGSCHMID HEINZ

IPC: G11C7/00 ,  G11C11/401 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4097 ,  H01L27/10

Abstract: Disclosed is a semiconductor memory (18, 20, 100, 200) having a hierarchical bit line architecture including local bit lines (LBL1, LBL2) on a lower fabrication layer, coupled to memory cells (MC), and master bit lines (MBL) on a higher fabrication layer, each coupled to an associated sense amplifier (SAi). Local bit lines disposed in any given column are coupled to different numbers of memory cells, i.e., the local bit lines have different lengths (L1, L2) over the memory cells. A hybrid configuration is preferably employed in which one local bit line (LBL1) in a column is directly coupled via a switch (251) to an associated sense amplifier, whereas the other local bit lines in the column (LBL2-LBL4) are operatively coupled to the sense amplifier via the master bit line. The different local bit line lengths are preferably selected such that total bit line capacitance with respect to any of the memory cells is substantially equalized, thereby improving data retention time for the memory.

公开(公告)号：DE69923097T2

公开(公告)日：2006-03-02

申请号：DE69923097

申请日：1999-03-09

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094

Abstract: There is disclosed a tri-state buffer circuit for receiving an input signal at a buffer input node and transmitting, responsive to a buffer enable signal, an output signal at a buffer output node. The buffer circuit includes an input stage (202) coupled to the buffer input node (208). The input stage (202) is configured to receive, when the buffer enable signal is enabled, the input signal. The buffer circuit further includes a level shifter stage (204) coupled to the input stage (202). The level shifter stage (204) is arranged to output, when the buffer enable signal is enabled, a set of level shifter stage control signals responsive to the input signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the input signal. The buffer circuit also includes an output stage (206) coupled to the level shifter stage (204). The output stage (206) is configured to output, when the buffer enable signal is enabled, the output signal (210) on the buffer output node responsive to the set of level shifter stage control signals. The voltage range of the output signal is lower than the voltage range of the set of level shifter stage control signals. The output stage (206) decouples the buffer output node from the input stage and the level shifter stage when the buffer enable signal is disabled.

公开(公告)号：DE102005033480A1

公开(公告)日：2006-02-16

申请号：DE102005033480

申请日：2005-07-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN DANIEL ,  MUELLER GERHARD

IPC: H01L27/22 ,  H01L43/08

Abstract: A magnetic tunnel junction (MTJ) device is configured to store at least two bits of data in a single cell utilizing the variable resistance characteristic of a MTJ. The MTJ includes a soft and two fixed magnetic layers with fixed field directions oriented in perpendicular directions. The soft magnetic layer is separated from the fixed layers by insulating layers preferably with different thicknesses, or with different material compositions. The resulting junction resistance can exhibit at least four distinct resistance values dependent on the magnetic orientation of the free magnetic layer. The cell is configured using a pattern with four lobes to store two bits, and eight lobes to store three bits. The resulting cell can be used to provide a fast, non-volatile magnetic random access memory (MRAM) with high density and no need to rewrite stored data after they are read, or as a fast galvanic isolator.