公开(公告)号：AU2003294845A8

公开(公告)日：2004-06-30

申请号：AU2003294845

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： PALM HERBERT ,  WILLER JOSEF ,  BOLLU MICHAEL ,  KOHLHASE ARMIN ,  LUDWIG CHRISTOPH

IPC: H01L21/8246 ,  H01L27/115

Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

公开(公告)号：ES2195616T3

公开(公告)日：2003-12-01

申请号：ES99948884

申请日：1999-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  SMOLA MICHAEL ,  WALLSTAB STEFAN

IPC: G01R31/28 ,  H01L21/822 ,  G01R31/317 ,  G01R31/3185 ,  H01L21/82 ,  H01L27/04

Abstract: The inventive circuit configuration has a plurality of function blocks (FB1...FBn), each function block being connected to at least one of the other function blocks and at least a portion of these connections being provided in the form of an interlocking element (SFF1...SFFm), which can be switched from normal mode to a test mode by means of an activation line (scan enable) and which has an additional data input and data output. These additional data inputs and data outputs are interconnected by data line sections (DL1...DLl) in such a way that the interlocking elements (SFF1...SFFm) form a shift register, which in turn forms a scan path. At least one electrically programmable fuse element (SE) is arranged along the activation line (scan enable) and/or the data line sections (DL1...DLl). This fuse element either interrupts the line concerned or connects it with a defined potential.

公开(公告)号：DE10208168C1

公开(公告)日：2003-08-14

申请号：DE10208168

申请日：2002-02-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER JUERGEN ,  PUESCHNER FRANK ,  WILLER JOSEF ,  PALM HERBERT

IPC: G06K19/077

Abstract: The structure includes a cover (20) over a recess (11). When the cover (20) is connected, the substrate (30) is held in the recess, along the base (12, 14, 15).

公开(公告)号：DE10108913A1

公开(公告)日：2002-09-12

申请号：DE10108913

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TADDIKEN HANS ,  WOHLRAB ERDMUTE ,  PALM HERBERT

IPC: G04F10/10 ,  G04F1/00 ,  G07F1/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  G04F10/00

Abstract: The invention relates to a time-detection device using a floating-gate-cell, wherein an ON-layer structure or a ONO-layer structure is provided between the floating-gate and the control-gate. A charge injection device is supplied in order to insert the floating-gate-electrode into the nitride layer of the ON-structure or the ONO-layer structure, wherein a voltage or a voltage pulse is applied to the control-gate-electrode, the centre of gravity of the charges injected into the nitride layer being located on the defining surface. Said time-detection device also comprises a device for detecting time elapsed since injection of the charges, based on changes in the transmission behaviour of the channel area, which are effected by displacement of the centre of gravity of the charges in the nitride layer away from the defining surface.

公开(公告)号：AT290243T

公开(公告)日：2005-03-15

申请号：AT02700209

申请日：2002-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  WOHLRAB ERDMUTE ,  TADDIKEN HANS

IPC: G04F10/10 ,  G04F1/00 ,  G07F1/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.

公开(公告)号：AT234472T

公开(公告)日：2003-03-15

申请号：AT99948884

申请日：1999-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  SMOLA MICHAEL ,  WALLSTAB STEFAN

IPC: H01L21/822 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H01L21/82 ,  H01L27/04

Abstract: The inventive circuit configuration has a plurality of function blocks (FB1...FBn), each function block being connected to at least one of the other function blocks and at least a portion of these connections being provided in the form of an interlocking element (SFF1...SFFm), which can be switched from normal mode to a test mode by means of an activation line (scan enable) and which has an additional data input and data output. These additional data inputs and data outputs are interconnected by data line sections (DL1...DLl) in such a way that the interlocking elements (SFF1...SFFm) form a shift register, which in turn forms a scan path. At least one electrically programmable fuse element (SE) is arranged along the activation line (scan enable) and/or the data line sections (DL1...DLl). This fuse element either interrupts the line concerned or connects it with a defined potential.

公开(公告)号：DE10129958A1

公开(公告)日：2003-01-09

申请号：DE10129958

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLER JOSEF ,  PALM HERBERT

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/788 ,  H01L29/792

Abstract: An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.

公开(公告)号：BR9914083A

公开(公告)日：2001-07-24

申请号：BR9914083

申请日：1999-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  SMOLA MICHAEL ,  WALLSTAB STEFAN

IPC: H01L21/822 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H01L21/82 ,  H01L27/04

Abstract: The inventive circuit configuration has a plurality of function blocks (FB1...FBn), each function block being connected to at least one of the other function blocks and at least a portion of these connections being provided in the form of an interlocking element (SFF1...SFFm), which can be switched from normal mode to a test mode by means of an activation line (scan enable) and which has an additional data input and data output. These additional data inputs and data outputs are interconnected by data line sections (DL1...DLl) in such a way that the interlocking elements (SFF1...SFFm) form a shift register, which in turn forms a scan path. At least one electrically programmable fuse element (SE) is arranged along the activation line (scan enable) and/or the data line sections (DL1...DLl). This fuse element either interrupts the line concerned or connects it with a defined potential.

公开(公告)号：DE10129958B4

公开(公告)日：2006-07-13

申请号：DE10129958

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLER JOSEF ,  PALM HERBERT

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/788 ,  H01L29/792

Abstract: An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.

公开(公告)号：DE10258194A1

公开(公告)日：2004-07-15

申请号：DE10258194

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES FLASH GM

Inventor： BOLLU MICHAEL ,  PALM HERBERT ,  WILLER JOSEF ,  LUDWIG CHRISTOPH ,  KOHLHASE ARMIN

IPC: H01L21/8246 ,  H01L27/115 ,  H01L21/8247

Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.