公开(公告)号：DE59912971D1

公开(公告)日：2006-02-02

申请号：DE59912971

申请日：1999-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAFFROTH THILO ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187

Abstract: An integrated circuit with BIST (built-in self-test) device (3) for carrying out a self-test of the integrated circuit (2) and includes a circuit unit (1) to be tested. One output of the BIST device (3) is connected to a contact point (4) of the circuit which serves for external contacting and which is connected to the input (In) of the circuit unit (1) to be tested. The BIST device (3) supplies a test signal (S1) to the circuit unit (1), via the contact point (4), the latter (4) being specifically connected via an input driver (D1) to the input (In) of the circuit unit (1).

公开(公告)号：DE10156830A1

公开(公告)日：2003-06-05

申请号：DE10156830

申请日：2001-11-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PETER JOERG ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN

IPC: G11C17/18 ,  H01L23/525

公开(公告)号：DE10119125C1

公开(公告)日：2002-12-12

申请号：DE10119125

申请日：2001-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C29/04 ,  G11C8/00 ,  G11C11/401 ,  G11C29/00

Abstract: A comparison method compares the address of a memory cell with a known address of a faulty memory cell in a semiconductor memory module. The module is subdivided into banks and has an address structure in which each address is associated with a bank that is organized in rows and columns and is defined by a row address, a column address and a bank address. Not only the row address is determined, but also the column address and the bank address when a memory access occurs. A bank is activated with a bank selection signal, and the access to a valid address of a faulty memory cell is indicated by an enable register.

公开(公告)号：DE10119144C1

公开(公告)日：2002-10-10

申请号：DE10119144

申请日：2001-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/12 ,  G11C29/40 ,  G11C29/44

Abstract: The data is stored in a memory bank having an addressable matrix structure. The elements selected from a group consisting of rows and columns, are subdivided into regions. The defect locations in each region are counted and compared with a threshold value. The comparison results are transmitted as an additional information along with the addresses of defect locations in the memory bank, to an external test device.

公开(公告)号：DE10063688A1

公开(公告)日：2002-07-18

申请号：DE10063688

申请日：2000-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  KAISER ROBERT

IPC: G11C17/16 ,  G11C17/18 ,  G11C29/00 ,  G11C17/14

Abstract: A circuit configuration for driving a programmable link has a volatile memory cell, which is coupled to the fuse for the permanent storage of data stored in the volatile memory, and also a shift register, which enables data to be read out from the volatile memory cell and data to be written to the memory cell. In this case, a plurality of shift registers may be interconnected to form a shift register chain for the purpose of driving a plurality of fuses. The shift register chain thus enables fast writing and reading to/from the volatile memory with a low outlay on circuitry.

公开(公告)号：DE10062092A1

公开(公告)日：2002-07-11

申请号：DE10062092

申请日：2000-12-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C29/44 ,  G11C29/00

Abstract: During a read routine at a location in a main memory area (1) a value is read out from a memory area and compared in a comparator (4) with a scheduled value from a scheduled value memory (5). By relying on a result from the comparison and on a read-mode control signal, the location is stored in an error location register (10). To test a memory area, a number of read routines are performed on the main memory area without storing the location in the error location store. A further read routine is carried out and the location is stored in the error location store depending on a result from the comparison. An Independent claim is also included for a method for testing a memory cell for a main memory area.

公开(公告)号：DE10062093A1

公开(公告)日：2002-05-02

申请号：DE10062093

申请日：2000-12-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/44

Abstract: The circuit comprises a comparator (4) for a data value with associated rated data value to determine a faulty address. The data value has been read-out of an addressed memory range of the memory field (1) during testing.The circuit has also a faulty address memory (9). Between the comparator and faulty address memory is fitted a switch (7) to deposit the address as faulty one in the faulty address memory, dependent on a control signal (Hit). Independent claims are included for an integrated circuit and method of faulty address suppression.

公开(公告)号：DE102006047410A1

公开(公告)日：2008-04-10

申请号：DE102006047410

申请日：2006-10-06

Applicant: QIMONDA AG ,  INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  SCHNABEL JOACHIM

IPC: H02M3/07

Abstract: The circuit (1) has a charge pump (100) switched on and off by a switching unit. Another switching unit is connected with an output of the pump at one end and with a supply potential at another end, where the switching units are n-or p-channel field effect transistors. A comparator (103) compares two potentials so that a signal is produced for controlling control inputs of the latter unit. An electrical circuit is supplied with an output voltage (Vneg) output by the pump, where the voltage is absolutely larger than a value of a supply voltage supplied by a circuit arrangement. An independent claim is also included for a method for operating a comparator for providing output signals.

公开(公告)号：DE10026276B4

公开(公告)日：2006-02-16

申请号：DE10026276

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN ,  SCHAFFROTH THILO

IPC: G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

Abstract: The explicit high voltage source (1) and internal low voltage source (2) are selectively connected to respective connection areas (4,5) of a programmable fuse (3) by respective connectors (6,7). The switches (8,9) connect the connectors to the connection areas, when a control signal is applied to the switches from a controller (16), to apply required voltage.

公开(公告)号：DE10260818A1

公开(公告)日：2004-07-15

申请号：DE10260818

申请日：2002-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  PETER JOERG

IPC: H01C17/26 ,  H01L21/02 ,  H01L27/08 ,  H01L23/525

Abstract: A process for adjusting a resistance in an integrated circuit, where the resistance has a resistive region (12) between two conductive regions (10,11) comprises passing a chosen programming current through the resistance to adjust it to a value depending on this current. Preferably the change is produced by electromigration. An Independent claim also included for a circuit for the above process.