公开(公告)号：JP2002063800A

公开(公告)日：2002-02-28

申请号：JP2001157851

申请日：2001-05-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRASS ECKHARD ,  SCHAFFROTH THILO ,  SCHNABEL JOACHIM ,  SCHNEIDER HELMUT

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/12 ,  G11C29/26 ,  H01L27/10 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for testing many word lines of a semiconductor memory assembly in a multiple WL wafer test in which a multiple wafer test can be performed quickly without needing much cost. SOLUTION: When an active word line(WL) is in a power-down state, a non-active word line is separated from negative VNWL voltage and made highly resistant immediately before the power-down of the active word line to prevent the rise of the non-active word line having negative voltage.

公开(公告)号：DE102006018921A1

公开(公告)日：2007-11-08

申请号：DE102006018921

申请日：2006-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEDER STEPHAN ,  SCHAFFROTH THILO ,  PROELL MANFRED ,  FISCHER FRANK

IPC: G11C29/08 ,  G11C11/406

Abstract: An integrated semiconductor memory with refreshing of memory cells includes a temperature sensor to detect a chip temperature of the integrated semiconductor memory, a connection to apply a command signal, a frequency generation unit to generate a frequency signal, and a memory cell to store a data item, the stored data item being refreshed at the frequency of the frequency signal. The frequency generation unit generates the frequency signal at a first frequency on the basis of a chip temperature detected by the temperature sensor when a first state of the command signal is applied and the frequency generation unit generates the frequency signal at a second frequency, which is changed in comparison with the first frequency, at the same chip temperature when a second state of the command signal is applied.

公开(公告)号：DE10120255C2

公开(公告)日：2003-03-20

申请号：DE10120255

申请日：2001-04-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DOLL ANDREAS ,  SCHAFFROTH THILO

IPC: G11C29/44 ,  G11C29/48 ,  G11C29/00

公开(公告)号：DE10101997A1

公开(公告)日：2003-02-06

申请号：DE10101997

申请日：2001-01-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAFFROTH THILO ,  SCHNABEL JOACHIM

IPC: G05F1/46 ,  H01L21/66 ,  H01L23/58

Abstract: An integrated circuit is supplied from a voltage source (92) through a supply circuit (2). A first internal voltage regulator (10) controls the voltages (V1,V2) for the useful circuit (1). A test control circuit (3) sets the reference voltage for a specific test mode through a trimming voltage value generator (50). This provides a trimming value (TSW) to a reference voltage regulator (30) for trimming the supply voltage to the voltage required for the particular test mode called for.

公开(公告)号：DE10120255A1

公开(公告)日：2002-11-07

申请号：DE10120255

申请日：2001-04-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DOLL ANDREAS ,  SCHAFFROTH THILO

IPC: G11C29/44 ,  G11C29/48 ,  G11C29/00

Abstract: An integrated semiconductor memory with a self test mode has a memory cell field (1) with row and column coders (2, 3) for selection of memory cells from the cell field as well as for read-write access, a test device (7) coupled to the memory cell field so that it can execute its function testing and a buffer memory (11) in which row and column data relating to defective memory cells is stored. Memory chip also has a parallel to serial converter (15) connected between the buffer memory and an input-output interface (16) of the memory for output of test data. The invention also relates to a corresponding test system (18) used with a semiconductor memory (17) that has an input-output interface that allows it to connect to a workstation for redundancy calculations.

公开(公告)号：DE50104949D1

公开(公告)日：2005-02-03

申请号：DE50104949

申请日：2001-08-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRISSOSTOMIDIS IOANNIS ,  SCHAFFROTH THILO ,  FISCHER DR

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C11/4091

Abstract: The circuit has a first current path for activation of the memory via an addressed word line, a second current path in which a read amplifier control signal is generated by a controler from a signal (RAVLD) derived from the first current path and a voltage supply device for components of the two current paths. Thick oxide transistors (T) supplied with an increased supply voltage are provided in the second path in addition to thin oxide transistors (T') supplied with a normal voltage.

公开(公告)号：DE10107182B4

公开(公告)日：2004-10-14

申请号：DE10107182

申请日：2001-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KEYSERLINGK ALBERT GRAF VON ,  SCHAFFROTH THILO ,  SCHNEIDER HELMUT

IPC: G11C11/408 ,  G11C8/08 ,  G11C11/407

公开(公告)号：DE10136703C1

公开(公告)日：2003-04-17

申请号：DE10136703

申请日：2001-07-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAFFROTH THILO

IPC: G01R31/317 ,  G01R31/3187 ,  G11C29/00

Abstract: A system for testing an integrated circuit at a plurality of locations with a plurality of test modes includes a sequence of test-mode storage devices, each of which has an input and an output. The sequence includes at least first and second test-mode storage devices located at corresponding first and second locations on the integrated circuit and configured to store first and second test modes. The first test-mode storage device is configured to perform a shift operation by providing the first test-mode at its output. The second test-mode storage device has its input connected to the output of the first test-mode storage device. This second device is configured to perform the shift operation by receiving, at its input, the first test mode and providing, at its output, the second test-mode.

公开(公告)号：DE10110626A1

公开(公告)日：2002-10-02

申请号：DE10110626

申请日：2001-03-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAFFROTH THILO ,  SCHNEIDER RALF

IPC: G01R21/10 ,  G01R31/28 ,  G01R15/04 ,  G01R19/165 ,  G01R31/26 ,  G11C29/00

公开(公告)号：DE10026276A1

公开(公告)日：2001-12-13

申请号：DE10026276

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN ,  SCHAFFROTH THILO

IPC: G11C17/18 ,  G11C16/02 ,  G11C17/16 ,  G11C29/00

Abstract: The explicit high voltage source (1) and internal low voltage source (2) are selectively connected to respective connection areas (4,5) of a programmable fuse (3) by respective connectors (6,7). The switches (8,9) connect the connectors to the connection areas, when a control signal is applied to the switches from a controller (16), to apply required voltage.