中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.045 seconds)

    11.
    发明专利
    未知

    公开(公告)号：DE10256487B4

    公开(公告)日：2008-12-24

    申请号：DE10256487

    申请日：2002-12-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RONZA MARIO DI ,  MARTELLONI YANNICK ,  SCHOEBER VOLKER

    IPC: G11C29/24 ,  G11C29/00 ,  G11C29/44

    Abstract: Method for testing an integrated circuit memory having a main memory (SP) with several data storage units, whereby test data is applied to a data storage unit and the output test data read from the main memory and compared in a self test unit (STE) with expected output test data. Any data differences are stored in a redundancy analysis memory (RAS) prior to analysis by a computer unit (RE). Based on the results of the analysis a repair strategy is determined involving redundant rows and/or columns. An Independent claim is made for an integrated memory with means for detection and correction of errors.

    14.
    发明专利
    未知

    公开(公告)号：DE10002139A1

    公开(公告)日：2001-08-02

    申请号：DE10002139

    申请日：2000-01-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PAUL STEFFEN ,  SCHOEBER VOLKER

    IPC: G11C29/00

    Abstract: A data memory comprising a main data memory (2) consisting of a plurality of data memory units, a redundancy data memory (3) consisting of several redundancy data memory units which replace defective data memory units of the main data memory (2), and a redundancy control logic (4) which is used to control access to the redundancy data memory (4). The main data memory (2) and the redundancy data memory (3) are connected in parallel to a data bus (6) by means of data lines (9,12). The main data memory (2) and the redundancy control logic are connected in parallel to an address bus (7) by means of address lines (10,15) in order to address data memory units in the data memory (1).

    17.
    发明专利
    未知

    公开(公告)号：DE10120282B4

    公开(公告)日：2005-08-18

    申请号：DE10120282

    申请日：2001-04-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： CATY OLIVIER ,  SCHOEBER VOLKER

    IPC: G06F13/40

    Abstract: The invention relates to an integrated bus signal hold cell that is coupled with a bus line via a common input/output, and that has at least two inverters for holding the last state of the bus line. The outputs of the inverters are coupled with each other's inputs, respectively. The input of the first inverter is coupled with the input/output. The output of the second inverter is coupled with the input/output. An additional input is provided via which the bus signal hold cell can be charged with a defined test signal. The invention also relates to an integrated bus system and a method for driving a bus signal hold cell and a bus system.

Patent Agency Ranking