公开(公告)号：DE10355509A1

公开(公告)日：2005-07-07

申请号：DE10355509

申请日：2003-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MARTELLONI YANNICK

IPC: G05F1/10 ,  H03K5/12 ,  H03K17/16 ,  H03K17/28 ,  H03K17/284

公开(公告)号：DE10256487B4

公开(公告)日：2008-12-24

申请号：DE10256487

申请日：2002-12-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RONZA MARIO DI ,  MARTELLONI YANNICK ,  SCHOEBER VOLKER

IPC: G11C29/24 ,  G11C29/00 ,  G11C29/44

Abstract: Method for testing an integrated circuit memory having a main memory (SP) with several data storage units, whereby test data is applied to a data storage unit and the output test data read from the main memory and compared in a self test unit (STE) with expected output test data. Any data differences are stored in a redundancy analysis memory (RAS) prior to analysis by a computer unit (RE). Based on the results of the analysis a repair strategy is determined involving redundant rows and/or columns. An Independent claim is made for an integrated memory with means for detection and correction of errors.

公开(公告)号：DE102004020306A1

公开(公告)日：2005-11-17

申请号：DE102004020306

申请日：2004-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MARTELLONI YANNICK ,  OSTERMAYR MARTIN

IPC: G11C8/00 ,  G11C17/08 ,  G11C17/12

公开(公告)号：DE10255102B3

公开(公告)日：2004-04-29

申请号：DE10255102

申请日：2002-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WICHT BERNHARD ,  NIRSCHL THOMAS ,  MARTELLONI YANNICK

IPC: G11C7/02 ,  G11C11/412 ,  G11C11/419 ,  H01L27/11

Abstract: The device is connected to at least one data line and has at least one memory node (K1,K2), at least one selection transistor (M5) connected to the first node, a first data line (BL), a first word line (WL1) and an arrangement (M7) for adapting the leakage current that causes a total leakage current from at least one bit line (BL) into the cell independent of the memory state of the cell, especially in the non-selected state.

公开(公告)号：DE50112519D1

公开(公告)日：2007-07-05

申请号：DE50112519

申请日：2001-02-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FLECK ROD ,  IENNE PAOLO ,  OBERLAENDER KLAUS ,  RANDHAWA SABEEN ,  GAZIELLO LAURENT ,  MARTELLONI YANNICK ,  PAUL STEFFEN ,  SCHOEBER VOLKER

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

Abstract: The testable read-only memory for data memory redundant logic has read-only memory units for storage of determined fault addresses of faulty data memory units. The serviceability of each read-only memory unit can be checked by application of input test data and by comparison of read output test data with expected nominal output test data.

公开(公告)号：DE102004052218B3

公开(公告)日：2006-04-27

申请号：DE102004052218

申请日：2004-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUPTA SIDDHARTH ,  MARTELLONI YANNICK

IPC: G11C17/12 ,  G11C5/06

Abstract: The assembly has memory cells (4), global and local voltage supply lines (6, 7), word lines (3) and bit lines (2). The global lines are run along the breadth of the assembly and parallel to the word lines. The local lines perpendicular to the word lines run parallel to the bit lines. The local lines run within blocks of the assembly such that global lines within the blocks are connected with the respective local lines.

公开(公告)号：DE112005002087A5

公开(公告)日：2007-07-19

申请号：DE112005002087

申请日：2005-08-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUPTA SIDDHARTH ,  LARGUIER JEAN-YVES ,  LEHMANN GUNTHER ,  MARTELLONI YANNICK

IPC: G11C17/18

公开(公告)号：DE102005029872A1

公开(公告)日：2007-04-19

申请号：DE102005029872

申请日：2005-06-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIRSCHL THOMAS ,  MARTELLONI YANNICK ,  OSTERMAYR MARTIN ,  HUBER PETER

IPC: G11C7/06 ,  G11C11/401 ,  H01L27/108

Abstract: The cell has three N-channel MOS transistors (11-13) and read terminals (2, 3) connected with read lines (5, 6). The cell is designed such that the information stored in the cell is detected by a differential read operation with which an electric current is evaluated between the read terminals during a read operation of the cell. A capacitor stores the information in the cell and a write terminal is connected with a write line. Independent claims are also included for the following: (1) a memory arrangement for reading and writing information; and (2) a reading device comprising input terminals.

公开(公告)号：DE102005045952B3

公开(公告)日：2007-01-25

申请号：DE102005045952

申请日：2005-09-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTHER ,  MARTELLONI YANNICK ,  GUPTA SIDDHARTH ,  DWIVEDI DEVESH

IPC: G11C7/12

Abstract: The method involves providing a bit line (6) and loading the bit line with an output potential. A read operation is performed for reading information over the bit line. Charging devices (13, 15) of the bit line are activated and deactivated based on potential of a virtual voltage supply line (4). The devices are deactivated only if a difference between a supply potential and the potential of the supply line falls below a preset value. Independent claims are also included for the following: (1) a memory arrangement with a charging device (2) a semiconductor circuit with a memory arrangement.

公开(公告)号：DE102004020306B4

公开(公告)日：2006-06-01

申请号：DE102004020306

申请日：2004-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MARTELLONI YANNICK ,  OSTERMAYR MARTIN

IPC: G11C17/12 ,  G11C8/00 ,  G11C17/08