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公开(公告)号：WO0154134A3
公开(公告)日：2002-03-28
申请号：PCT/EP0100295
申请日：2001-01-11
Applicant: INFINEON TECHNOLOGIES AG , PAUL STEFFEN , SCHOEBER VOLKER
Inventor： PAUL STEFFEN , SCHOEBER VOLKER
CPC classification number: G11C29/44
Abstract: The invention relates to a test method for testing a data memory which comprises a main data memory (2) with a plurality of data memory units. According to the inventive method, the following steps are carried out for all data memory units: (a) addressing a data memory unit by applying the address of the data memory unit to a data bus linked with the main data memory (2); (b) applying the input test data for testing the addressed data memory unit to a data bus linked with the main data memory (2); (c) reading out the read-out test data from the addressed data memory unit; (d) comparing the output test data with the expected scheduled output test data; (e) writing the applied address into an address memory unit of an address memory (5) and the expected scheduled output test data into a pertaining redundancy data memory unit of a redundancy data memory (6) if the output test data and the expected scheduled output test data do not correspond.
Abstract translation: 用于测试具有具有多个数据存储单元，其中，对于所有的数据存储单元中的以下步骤进行的主存储器（2）一个数据存储器试验方法：（a）以与主数据存储器将所述数据存储单元的地址的寻址的数据存储单元（2） 相关联的地址总线; （B）数据在相关联，用于被寻址的数据存储单元的测试输入的测试数据应用到主数据存储器（2）; （C）读出从被寻址的数据存储单元输出的测试数据; （D）比较预期标称输出的测试数据输出测试数据; （E）在冗余数据存储器中的相关联的冗余数据存储单元（6），当输出测试数据与预期标称输出测试数据不匹配写在一个地址存储器（5）和预期标称输出的测试数据的一个地址存储单元所施加的地址。
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公开(公告)号：WO0106651A3
公开(公告)日：2001-05-10
申请号：PCT/DE0002082
申请日：2000-06-27
Applicant: INFINEON TECHNOLOGIES AG , SCHOEBER VOLKER , DIRSCHERL GERD , PAPELITZKY ERWIN
Inventor： SCHOEBER VOLKER , DIRSCHERL GERD , PAPELITZKY ERWIN
IPC: H03K19/007 , H03K19/003
CPC classification number: H03K19/007
Abstract: The invention relates to an integrated semiconductor circuit, comprising at least one partial circuit which has a pull-down branch with at least one NMOS transistor (T3, T4) and a pull-up branch with at least two PMOS transistors (T1, T2) connected in series, whereby the junction between the pull-down and the pull-up branches forms an output connection (A) for the partial circuit. The elements of the pull-down (T3, T4) and pull-up (T1, T2) branches are configured in such a way that the current output of the pull-down branch is less than that of the pull-up branch.
Abstract translation: 具有至少一个子电路，其包括与至少一个NMOS晶体管（T3，T4）和具有至少两个串联连接的PMOS晶体管上拉分支（T1，T2），其中，所述下拉支路的半导体集成电路 的输出端子的下拉和上拉分支（a）中的部分电路的，所述下拉的元件（T3，T4）和上拉分支（T1，T2）设计成之间的连接点 是下拉分支的当前产量小于上拉分支的产量。
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公开(公告)号：WO0153944A3
公开(公告)日：2002-02-14
申请号：PCT/EP0100075
申请日：2001-01-05
Applicant: INFINEON TECHNOLOGIES AG , PAUL STEFFEN , SCHOEBER VOLKER
Inventor： PAUL STEFFEN , SCHOEBER VOLKER
CPC classification number: G11C29/789 , G11C29/846
Abstract: A data memory comprising a main data memory (2) consisting of a plurality of data memory units, a redundant data memory (3) consisting of several redundant data memory units which replace defective data memory units of the main data memory (2), and a redundant control logic (4) which is used to control access to the redundant data memory (4). The main data memory (2) and the redundant data memory (3) are connected in parallel to a data bus (6) by means of data lines (9,12). The main data memory (2) and the redundant control logic are connected in parallel to an address bus (7) by means of address lines (10,15) in order to address data memory units in the data memory (1).
Abstract translation: 与由多个数据存储单元中的主数据存储装置（2），冗余数据存储器（3）由多个冗余数据存储单元中的用于替换的主数据存储器（2）的有故障的数据存储器单元，以及（具有冗余控制逻辑的一组数据存储器 4）连接，用于控制访问冗余数据存储器（3），其中，所述主数据存储装置（2）和平行经由数据线（9,12）中的冗余数据存储器（3）的数据总线（6），和 其中，所述主数据存储装置（2）和所述冗余控制逻辑平行于经由地址线彼此（10，15）（4）到地址总线（7），用于在所述数据存储器（1）的数据存储单元寻址连接。
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4.发明申请
公开(公告)号：WO0127761A3
公开(公告)日：2001-10-11
申请号：PCT/EP0009963
申请日：2000-10-10
Applicant: INFINEON TECHNOLOGIES AG , SCHOEBER VOLKER
Inventor： SCHOEBER VOLKER
IPC: G01R31/3181 , G01R31/3185 , G06F11/277
CPC classification number: G01R31/318541 , G01R31/31813 , G01R31/318547 , G06F11/277
Abstract: The invention relates to a circuit cell for test pattern generation and test pattern compression of circuits with inbuilt self test functions which have a test data coupling circuit (6) comprising a test data input (5) for receiving a test data input signal TDI of an upstream circuit cell which can be saved in a test data intermediate memory, a data input (8) for applying a data input signal TDI which can be stored in a data intermediate memory, a test data output (15) for transmission of the intermediate stored test data signal TDI and a data output (16) for transmission of the intermediate-stored data output signal D to a data signal path via a data signal output (51) memories for the circuit cell. Both intermediate stores pertaining to the test data coupling circuit (6) have a common feedback signal path via which the received test data input signal TDI can be coupled to the data signal path depending on a first generated control signal TEST which can be coupled to the first data coupling circuit (6). A logical, comparitive circuit (26) is also provided which compares the test data input signal TDI with that of a transferred test data signal TD transferred from the test data coupling circuit (6) in order to generate a comparative signal which is transferred to a circuit device (21). Depending on a second control signal SCAN, the circuit device (21) transfers the generated comparative signal or the test data signal TD emitted by the test data coupling circuit to a test data signal output (48) pertaining to the circuit cell.
Abstract translation: 为测试模式生成和电路与（6），其具有测试数据输入，用于从上游连接的电路单元，其被存储在测试数据接收测试数据输入信号TDI（5）内建自测试功能，测试数据耦合电路测试模式压缩电路单元锁存器，一个 数据输入（8），用于经由数据信号输出缓冲器存储的数据信号d输出到数据信号路径施加数据输入信号DI，其被存储在一个数据锁存器，测试数据输出（15），用于分配所述暂时存储的测试数据信号TD，和数据输出（16）（51 ），其具有测试数据耦合电路的两个锁存器的电路单元（6）具有通过其在所述数据信号路径施加接收到的测试数据输入信号TDI响应于（在测试数据耦合电路6）开始步骤的公共反馈信号路径 uersignal TEST可以耦合。 这也是一个逻辑比较电路（26）设置，所述测试数据信号，与该测试数据耦合电路（6），用于产生一个比较信号进行比较，其响应施加到开关装置（21）的第二控制信号SCAN TD分配的测试数据输入信号TDI 产生的比较信号或所述测试数据耦合电路（6）输出的测试数据信号TD到电路单元的测试数据信号输出（48）接通。
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公开(公告)号：DE10002127B4
公开(公告)日：2012-12-27
申请号：DE10002127
申请日：2000-01-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： PAUL STEFFEN DR , SCHOEBER VOLKER
Abstract: Testverfahren zum Testen eines Datenspeichers, der einen Hauptdatenspeicher (2) mit einer Vielzahl von Datenspeichereinheiten aufweist, bei dem die folgenden Schritte für alle Datenspeichereinheiten durchgeführt werden: (a) Adressieren einer Datenspeichereinheit durch Anlegen der Adresse der Datenspeichereinheit an einen mit dem Hauptdatenspeicher (2) verbundenen Adreßbus; (b) Anlegen von Eingabetestdaten zum Testen der adressierten Datenspeichereinheit an einen mit dem Hauptdatenspeicher (2) verbundenen Datenbus; (c) Auslesen von Ausgabetestdaten aus der adressierten Datenspeichereinheit; (d) Vergleichen der Ausgabetestdaten mit erwarteten Soll-Ausgabetestdaten; (e) Einschreiben der angelegten Adresse in eine Adressenspeichereinheit eines Adressenspeichers (5) und der erwarteten Soll-Ausgabetestdaten in eine zugeordnete Redundanz-Datenspeichereinheit eines Redundanz-Datenspeichers (6), wenn die Ausgabetestdaten und die erwarteten Soll-Ausgabetestdaten nicht übereinstimmen.
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Patent Agency Ranking
公开(公告)号：DE50112519D1
公开(公告)日：2007-07-05
申请号：DE50112519
申请日：2001-02-05
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FLECK ROD , IENNE PAOLO , OBERLAENDER KLAUS , RANDHAWA SABEEN , GAZIELLO LAURENT , MARTELLONI YANNICK , PAUL STEFFEN , SCHOEBER VOLKER
Abstract: The testable read-only memory for data memory redundant logic has read-only memory units for storage of determined fault addresses of faulty data memory units. The serviceability of each read-only memory unit can be checked by application of input test data and by comparison of read output test data with expected nominal output test data.
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公开(公告)号：DE10256487A1
公开(公告)日：2004-07-08
申请号：DE10256487
申请日：2002-12-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： RONZA MARIO DI , MARTELLONI YANNICK , SCHOEBER VOLKER
Abstract: Method for testing an integrated circuit memory having a main memory (SP) with several data storage units, whereby test data is applied to a data storage unit and the output test data read from the main memory and compared in a self test unit (STE) with expected output test data. Any data differences are stored in a redundancy analysis memory (RAS) prior to analysis by a computer unit (RE). Based on the results of the analysis a repair strategy is determined involving redundant rows and/or columns. An Independent claim is made for an integrated memory with means for detection and correction of errors.
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公开(公告)号：DE10155620A1
公开(公告)日：2003-05-28
申请号：DE10155620
申请日：2001-11-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHOEBER VOLKER , DI RONZA MARIO , PICOT OLIVIER
Abstract: The device has at least one fuse housing (10) with a number of programmable fuse elements and a number of integrated circuit modules (DRM) or modules of integrated circuits, each with a number of module elements and at least one adjustable module element. The fuse box is electrically connected to the integrated circuit modules and the adjustable module element can beset up by programming the fuse element.
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公开(公告)号：DE10002127A1
公开(公告)日：2001-08-02
申请号：DE10002127
申请日：2000-01-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： PAUL STEFFEN , SCHOEBER VOLKER
Abstract: The invention relates to a test method for testing a data memory which comprises a main data memory (2) with a plurality of data memory units. According to the inventive method, the following steps are carried out for all data memory units: (a) addressing a data memory unit by applying the address of the data memory unit to a data bus linked with the main data memory (2); (b) applying the input test data for testing the addressed data memory unit to a data bus linked with the main data memory (2); (c) reading out the read-out test data from the addressed data memory unit; (d) comparing the output test data with the expected scheduled output test data; (e) writing the applied address into an address memory unit of an address memory (5) and the expected scheduled output test data into a pertaining redundancy data memory unit of a redundancy data memory (6) if the output test data and the expected scheduled output test data do not correspond.
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公开(公告)号：DE19948904C1
公开(公告)日：2001-07-05
申请号：DE19948904
申请日：1999-10-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHOEBER VOLKER
IPC: G01R31/3185 , G06F11/267 , G01R31/3187
Abstract: The method involves initializing one circuit cell as a test-pattern transmitting circuit cell, and one cell as a test-pattern receiving circuit cell. A generated test pattern is applied to the combinational circuit (3) for data processing by a memory unit of the test pattern transmitting circuit cell. Test data are read from the memory unit of the test pattern receiving cell by an automatic tester. An Independent claim is included for a circuit cell in an integrated circuit with a built-in self-test function.
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