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    Memory device provided with fuse memory element
    1.
    发明专利
    Memory device provided with fuse memory element 有权
    带有保险丝存储元件的存储器件

    公开(公告)号：JP2007172821A

    公开(公告)日：2007-07-05

    申请号：JP2006343948

    申请日：2006-12-21

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： GUNTHER LEHMANN ,  DIEL MICHAEL ,  DI RONZA MARIO

    IPC: G11C17/14

    CPC classification number: G11C17/18 ,  G11C5/14

    Abstract: PROBLEM TO BE SOLVED: To provide a fuse memory element in which power consumption is reduced. SOLUTION: A memory device (200) is provided with nonvolatile memory elements (211, 221, 231), readout circuits (212, 222, 232) for reading out memory information items stored in this memory elements (211, 221, 231), switching units (240) applying supply power source voltage (VDD_global) to the read-out circuits (212, 222, 232), and a control unit (241) controlling the switching units (240) by a method in accordance with the memory information stored in the memory elements (211, 221, 231). COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供功耗降低的熔丝存储元件。 存储器件（200）具有非易失性存储元件（211,221,231），用于读出存储在该存储器元件（211,221,221）中的存储器信息项的读出电路（212,222,232） 231），将电源电压（VDD_global）施加到读出电路（212,222,232）的开关单元（240）和控制单元（241），控制单元（241）通过根据 所述存储器信息存储在所述存储元件（211,221,231）中。 版权所有（C）2007，JPO＆INPIT

    2.
    发明专利
    未知

    公开(公告)号：DE60320745D1

    公开(公告)日：2008-06-19

    申请号：DE60320745

    申请日：2003-02-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DI RONZA MARIO ,  MARTELLONI YANNICK

    IPC: G11C29/00 ,  H02H3/05

    Abstract: A method for repairing a memory comprising a Memory Built-In Self Repair (MBISR) structure comprises the steps of detection of defective storage cells, and redundancy allocation. The redundancy allocation step is carried out in such a way that it combines a row and/or column oriented redundancy repair approach vaith a word oriented redundancy repair approach. A Memory Built-In Self Repair (MBISR) device comprises at least one memory (2) with row and/or column redundancy, at least one row and/or column Memory Built-In Self Repair (MBISR) circuit (3), and a word redundancy block (4). Furthermore, a distributed MBISR structure as well as dedicated Column/Row MBISR circuits (3) are provided.

    6.
    发明专利
    未知

    公开(公告)号：DE10334520B4

    公开(公告)日：2008-08-21

    申请号：DE10334520

    申请日：2003-07-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DI RONZA MARIO ,  OLBRICH ALEXANDER

    IPC: G11C29/24 ,  G06F11/00 ,  G11C29/00

    Abstract: An error-correction process for a digital memory (1) with individually addressable memory words, by which a detected faulty memory word is substituted by another word, comprises different write input (2) and read output (3) lines such that a written word is read, outputted and recognized as defective if it differs from the original. An independent claim is also included for a memory device for the above process.

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