公开(公告)号：DE112007000267B4

公开(公告)日：2017-11-09

申请号：DE112007000267

申请日：2007-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS

IPC: H01L21/60 ,  H01L23/50

Abstract: Verfahren zur Herstellung einer Halbleiteranordnung mit den Schritten: Herstellen eines ersten integrierten Schaltkreises (250a); Herstellen eines zweiten integrierten Schaltkreises (250b); und vertikales Koppeln des zweiten integrierten Schaltkreises (250b) an den ersten integrierten Schaltkreis (250a), wobei das Herstellen des ersten integrierten Schaltkreises (250a) ein Bereitstellen eines ersten Werkstücks (201a), ein Ausbilden zumindest eines ersten aktiven Gebiets (222a, 224a) innerhalb des ersten Werkstücks (201a) und ein Ausbilden zumindest eines tiefen Vias (240a, 242a) innerhalb des ersten Werkstücks (201a) vor dem Ausbilden des aktiven Gebiets des ersten integrierten Schaltkreises (250a) umfasst, wobei das zumindest eine tiefe Via (240a, 242a) eine vertikale elektrische Verbindung für den ersten integrierten Schaltkreis (250a) bereitstellt.

公开(公告)号：DE10360537A1

公开(公告)日：2004-08-05

申请号：DE10360537

申请日：2003-12-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  WISE MICHAEL

IPC: H01L21/762 ,  H01L27/108

Abstract: A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation trenches are partially filled with a first dielectric material. An etch mask layer is deposited on the substrate and used to remove excess first dielectric material on the surface of the substrate. The isolation trenches are then completely filled with a second dielectric material. Excess second dielectric material is then removed from the surface of the substrate.

公开(公告)号：DE112007000267T5

公开(公告)日：2009-01-22

申请号：DE112007000267

申请日：2007-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065

Abstract: Vertically stacked integrated circuits and methods of fabrication thereof are disclosed. Deep vias that provide vertical electrical connection for vertically stacked integrated circuits are formed early in the manufacturing process, before integrated circuits are bonded together to form a three dimensional integrated circuit (3D-IC).

公开(公告)号：WO0229888A3

公开(公告)日：2002-08-29

申请号：PCT/US0127366

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KNORR ANDREAS ,  ECONOMIKOS LAERTIS ,  HALLE SCOTT

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10891

Abstract: A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride (16) remaining in place. Once the devices have been formed and the gate polysilicon (18) has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide (21) fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.

Abstract translation: 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成具有衬垫氮化物（16）保持就位的垂直器件而形成。 一旦器件已经形成并且栅极多晶硅（18）已被平坦化到衬垫氮化物的表面，衬垫氮化物被剥离，留下栅极多晶硅插塞的顶部延伸到有源硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物（21）填充多晶硅插塞之间和之上的区域。 顶部氧化物被平坦化回到多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

公开(公告)号：DE102004001099B4

公开(公告)日：2009-12-31

申请号：DE102004001099

申请日：2004-01-05

Applicant: QIMONDA AG ,  IBM

Inventor： BELYANSKY MICHAEL ,  GLUSCHENKOV OLEG ,  KNORR ANDREAS

IPC: H01L21/316 ,  C23C8/06 ,  C23C8/12 ,  C23C8/36 ,  H01L21/473 ,  H05H1/46

Abstract: A method of oxidizing a substrate having area of about 30,000 mm 2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal silicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1 e12 cm -3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.

公开(公告)号：DE10214743A1

公开(公告)日：2004-11-04

申请号：DE10214743

申请日：2002-04-03

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KNORR ANDREAS ,  KUDELKA STEPHAN ,  MANDELMAN JACK ,  RAHN STEPHAN ,  TEWS HELMUT ,  WISE MICHAEL

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108