公开(公告)号：JP2000323684A

公开(公告)日：2000-11-24

申请号：JP2000085406

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  HALLE SCOTT ,  RADENS CARL J ,  JEFFREY J WERSER ,  BEINTNER JOCHEN ,  MANDELMAN JACK A ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a trench capacitor in a semiconductor body. SOLUTION: A trench capacitor 10 and a MOS transistor 9 are provided in a substrate 16 to form a cell 8 of the DRAM, and the cell 8 is separated from adjacent cells by an STI region 28. The capacitor 10 is composed of an insulator 14 enveloping the trench and a first electrode 24 filled with polysilicon 12, is connected to the drain portion 72 through a buried electrode 22, and is insulated from a gate electrode 20 by a dielectric 23. A second electrode 25 is formed in its bottom portion through an insulator 14. A transistor 9 has N-type drain 72 and source 71 in an upper active region 11 of the substrate 16 and operates with a p well as channel.

公开(公告)号：WO0229888A3

公开(公告)日：2002-08-29

申请号：PCT/US0127366

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KNORR ANDREAS ,  ECONOMIKOS LAERTIS ,  HALLE SCOTT

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10891

Abstract: A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride (16) remaining in place. Once the devices have been formed and the gate polysilicon (18) has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide (21) fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.

Abstract translation: 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成具有衬垫氮化物（16）保持就位的垂直器件而形成。 一旦器件已经形成并且栅极多晶硅（18）已被平坦化到衬垫氮化物的表面，衬垫氮化物被剥离，留下栅极多晶硅插塞的顶部延伸到有源硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物（21）填充多晶硅插塞之间和之上的区域。 顶部氧化物被平坦化回到多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

公开(公告)号：WO0118863A9

公开(公告)日：2002-11-07

申请号：PCT/US0024402

申请日：2000-09-06

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BRINTZINGER AXEL ,  GAMBINO JEFFREY ,  RUPP THOMAS ,  HALLE SCOTT

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In order to form a cavity for a fusible link in a semiconductor device, an etchable material is applied over and around a portion of the fusible link and the etchable material is coated with a protection layer. The access abutting the etchable material is formed through the protection layer. After the removal of the etchable material, the access is partially filled with a refilling material to thereby form the cavity.

Abstract translation: 为了在半导体器件中形成用于可熔连接件的空腔，可蚀刻材料施加在可熔连接件的一部分上和周围，并且可蚀刻材料被涂覆有保护层。 通过保护层形成邻接可蚀刻材料的通路。 在去除可蚀刻材料之后，进入部分地填充有填充材料，从而形成空腔。