公开(公告)号：DE60103624T2

公开(公告)日：2005-08-25

申请号：DE60103624

申请日：2001-03-15

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： WEINFURTNER OLIVER

IPC: G11C5/14 ,  G11C11/00

Abstract: In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. An evaluation arrangement evaluates a combination of only a predetermined one of a plurality of N input signals from remote devices, and only a predetermined one of a plurality of X state signals indicating a current state in the state diagram at any instant of time. The controller generates a plurality of Y output signals having a predetermined logical value that indicates that a change from one state to a next state in the state diagram is to be made when the predetermined one of both the plurality of N input signals and the plurality of X state signals comprise a predetermined logical value. A state storage device is responsive to the predetermined one of a plurality of Y output signals having a predetermined logical value, and generates a revised plurality of X state output signals for transmission back to the evaluation arrangement indicating a change in the state diagram from a current state to a next state of the plurality of X states. An output arrangement is responsive to the revised plurality of X state output signals for generating separate predetermined ones of M output signals to remote devices associated with said next state for controlling the generator system.

公开(公告)号：JP2002319282A

公开(公告)日：2002-10-31

申请号：JP2002002498

申请日：2002-01-09

Applicant: IBM

Inventor： LOUIS LU-CHEN HSU ,  FRANKOWSKY GERD ,  WEINFURTNER OLIVER

IPC: G11C11/407 ,  G06F15/78 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To provide a leak monitor element and a method improved for a DRAM. SOLUTION: A refresh-cycle time is directly adjusted based on a cell leakage state. In a method for designing a low power leakage monitor element, a memory cell being the same as a cell in an actual array is used. This monitor cell is designed so as to indicate an average cell or the worst state of cell leakage state. When leakage is severe, a refresh-cycle time is shortened greatly, for example, to a half. When a leakage level is very low or is undetectable, a refresh-cycle time is increased by a large amount for example, to twice. When leakage is normal or within a normal range, a refresh-cycle time is optimized, and power consumption used for DRAM refreshing is minimized.

公开(公告)号：DE60011471T2

公开(公告)日：2005-06-09

申请号：DE60011471

申请日：2000-12-13

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HSU L ,  WEINFURTNER OLIVER ,  WORDEMAN R

IPC: H02M3/07

Abstract: A charge pump generator system and method is provided which more precisely maintains the level of an internally generated voltage supply by operating some or all of the available charge pumps depending upon the voltage level reached by the voltage supply. When the voltage supply is far from its target level, a first group and a second group of charge pumps are operated. The first group may preferably have a faster pumping rate or a greater number of charge pumps than the second group. When the voltage supply exceeds a first predetermined level, the first group of charge pumps is switched off while the second group remains on, such that the rate of charge transfer slows. The second group continues operating until a second, e.g. target, voltage level is exceeded. The slower rate of charge transfer then effective reduces overshoot, ringing and noise coupled onto the voltage supply line. Preferably, at least one charge pump operates in both standby and active modes, thereby reducing chip area.

公开(公告)号：DE60101475T2

公开(公告)日：2004-11-25

申请号：DE60101475

申请日：2001-05-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU L ,  WEINFURTNER OLIVER ,  JI L

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

公开(公告)号：DE60101475D1

公开(公告)日：2004-01-22

申请号：DE60101475

申请日：2001-05-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU L ,  WEINFURTNER OLIVER ,  JI L

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.