公开(公告)号：JP2007158330A

公开(公告)日：2007-06-21

申请号：JP2006317786

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  LOUIS LU-CHEN HSU ,  YANG CHIH-CHAO ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/786

CPC classification number: H01L23/5256 ,  H01L21/268 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure including at least one e-fuse, and a manufacturing method which is easily integrated with standard semiconductor technologies, thus minimizing implementation costs. SOLUTION: A semiconductor structure includes at least one e-fuse embedded in a trench that is located in a semiconductor substrate (a bulk or semiconductor-on-insulator substrate). According to the present invention, the e-fuse is in electrical contact with a dopant region that is located in the semiconductor substrate. The present invention also provides a method of manufacturing the semiconductor structure in which the embedded e-fuse and trench isolation regions are formed almost at the same time. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供包括至少一个电熔丝的半导体结构和容易与标准半导体技术集成的制造方法，从而最小化实施成本。 解决方案：半导体结构包括嵌入在半导体衬底（主体或绝缘体上半导体衬底）上的沟槽中的至少一个电熔丝。 根据本发明，电熔丝与位于半导体衬底中的掺杂区电接触。 本发明还提供了一种制造半导体结构的方法，其中嵌入式电熔丝和沟槽隔离区几乎同时形成。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2002319282A

公开(公告)日：2002-10-31

申请号：JP2002002498

申请日：2002-01-09

Applicant: IBM

Inventor： LOUIS LU-CHEN HSU ,  FRANKOWSKY GERD ,  WEINFURTNER OLIVER

IPC: G11C11/407 ,  G06F15/78 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To provide a leak monitor element and a method improved for a DRAM. SOLUTION: A refresh-cycle time is directly adjusted based on a cell leakage state. In a method for designing a low power leakage monitor element, a memory cell being the same as a cell in an actual array is used. This monitor cell is designed so as to indicate an average cell or the worst state of cell leakage state. When leakage is severe, a refresh-cycle time is shortened greatly, for example, to a half. When a leakage level is very low or is undetectable, a refresh-cycle time is increased by a large amount for example, to twice. When leakage is normal or within a normal range, a refresh-cycle time is optimized, and power consumption used for DRAM refreshing is minimized.

公开(公告)号：JP2008219002A

公开(公告)日：2008-09-18

申请号：JP2008035478

申请日：2008-02-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  LOUIS LU-CHEN HSU ,  CHENG KANGGUO ,  SHEETS JOHN EDWARD II

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66818

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a FinFET having a short fin having a uniform width. SOLUTION: There are provided a fin with a comparatively uniform width in a fin-type field effect transistor (FinFET) 100 and a device and a method for forming the same. A fin structure 110 can be formed so that the surface of a sidewall part of the fin structure is vertical with respect to a first crystal direction. A tapered region at the end portion of the fin structure can be vertical with respect to a second crystal direction. The fin structure can be subjected to a crystal-dependent etching. For a crystal-dependent etching, a material can be removed relatively quickly from the part of the fin vertical to the second crystal direction, and due to this, a fin structure with a comparatively uniform width can be brought about. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种形成具有均匀宽度的短鳍的FinFET的方法。 解决方案：在翅片型场效应晶体管（FinFET）100中提供了具有相对均匀宽度的鳍片，以及用于形成该鳍片的器件及其方法。 翅片结构110可以形成为使翅片结构的侧壁部分的表面相对于第一晶体方向垂直。 翅片结构的端部处的锥形区域可相对于第二晶体方向垂直。 翅片结构可以进行晶体依赖蚀刻。 对于晶体依赖的蚀刻，可以从翅片垂直于第二晶体方向的部分相对快速地去除材料，并且由此可以产生具有相对均匀的宽度的翅片结构。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：MY116040A

公开(公告)日：2003-10-31

申请号：MYPI19993047

申请日：1999-07-20

Applicant: IBM

Inventor： FARIBORZ ASSADERAGHI ,  CLAUDE L BERTIN ,  JEFFREY P GAMBINO ,  LOUIS LU-CHEN HSU ,  JACK ALLAN MANDELMAN

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/84 ,  H01L27/108 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: AN ACTIVE FET BODY DEVICE WHICH COMPRISES AN ACTIVE FET REGION INCLUDING A GATE (13, 15, 16,24,26,28,30,3 I), A BODY REGION (4) AND ELECTRICAL CONNECTION BETWEEN SAID GATE AND SAID BODY REGION THAT IS LOCATED WITHIN THE ACTIVE FET REGION IS PROVIDED ALONG WITH VARIOUS METHODS FOR FABRICATING THE DEVICES. THE ELECTRICAL CONNECTION EXTENDS OVER SUBSTANTIALLY THE ENTIRE WIDTH OF THE FET. (FIGURE 6)