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    METHOD FOR ADJUSTING DYNAMIC DRAM REFRESH-RATE BASED ON CELL LEAK MONITOR
    2.
    发明专利
    METHOD FOR ADJUSTING DYNAMIC DRAM REFRESH-RATE BASED ON CELL LEAK MONITOR 审中-公开

    公开(公告)号：JP2002319282A

    公开(公告)日：2002-10-31

    申请号：JP2002002498

    申请日：2002-01-09

    Applicant: IBM

    Inventor： LOUIS LU-CHEN HSU ,  FRANKOWSKY GERD ,  WEINFURTNER OLIVER

    IPC: G11C11/407 ,  G06F15/78 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406

    Abstract: PROBLEM TO BE SOLVED: To provide a leak monitor element and a method improved for a DRAM. SOLUTION: A refresh-cycle time is directly adjusted based on a cell leakage state. In a method for designing a low power leakage monitor element, a memory cell being the same as a cell in an actual array is used. This monitor cell is designed so as to indicate an average cell or the worst state of cell leakage state. When leakage is severe, a refresh-cycle time is shortened greatly, for example, to a half. When a leakage level is very low or is undetectable, a refresh-cycle time is increased by a large amount for example, to twice. When leakage is normal or within a normal range, a refresh-cycle time is optimized, and power consumption used for DRAM refreshing is minimized.

    DYNAMIC DRAM REFRESH RATE ADJUSTMENT BASED ON CELL LEAKAGE MONITORING
    3.
    发明申请
    DYNAMIC DRAM REFRESH RATE ADJUSTMENT BASED ON CELL LEAKAGE MONITORING 审中-公开
    基于电池泄漏监测的动态DRAM刷新率调整

    公开(公告)号：WO02058072A3

    公开(公告)日：2002-09-26

    申请号：PCT/US0201406

    申请日：2002-01-16

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： HSU LOUIS ,  FRANKOWSKY GERD ,  WEINFURTNER OLIVER

    IPC: G11C11/407 ,  G06F15/78 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406

    CPC classification number: G11C11/406 ,  G11C2207/104 ,  G11C2207/2254

    Abstract: A novel DRAM refresh method and system and a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the refresh cycle time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the real array. This monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized. The advantages of this method over the existing method, that is, adjusting the refresh cycle time based on chip temperature include (1) the contributions from non-temperature dependent leakage factors are taken into consideration, (2) the present invention does not require different process steps, or extra process costs to integrate such device in the chip, and (3) the present invention is a straight forward method, the monitor cell does not need any calibration. In addition, its leakage mechanism and reliability concern are all identical to the cells in a real array.

    Abstract translation: 一种新颖的DRAM刷新方法和系统以及设计低功耗漏电监测装置的新方法。 利用DRAM刷新方法，基于单元泄漏条件来调整刷新周期时间。 设计低功率泄漏监测装置的方法使用与真实阵列中的单元相同的存储单元。 该监视器单元被设计成它将代表平均单元或最坏的单元泄漏状况。 如果泄漏严重，则刷新周期时间会显着减少或减半。 如果泄漏电平非常低或不可检测，则刷新周期时间显着增加或加倍。 如果泄漏中等或在正常范围内，则刷新时间被优化，使得用于DRAM刷新的功耗最小化。 该方法优于现有方法，即基于芯片温度调整刷新周期时间的优点包括：（1）考虑到非温度依赖性泄漏因素的贡献，（2）本发明不需要不同的 处理步骤或额外的处理成本，以及（3）本发明是一种直接的方法，监测单元不需要任何校准。 此外，其泄漏机制和可靠性问题与实际阵列中的单元格完全相同。

    8.
    发明专利
    未知

    公开(公告)号：DE10261327A1

    公开(公告)日：2003-08-07

    申请号：DE10261327

    申请日：2002-12-27

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： FRANKOWSKY GERD ,  HOKENMAIER WOLFGANG ,  HANSON DAVID R ,  LEHMANN GUNTHER

    IPC: G11C7/18 ,  G11C11/4097 ,  G11C29/00

    Abstract: A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.

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