公开(公告)号：DE112005001686T5

公开(公告)日：2007-06-06

申请号：DE112005001686

申请日：2005-07-08

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  OSBURN EDWARD

IPC: H05K1/02 ,  H05K1/18

Abstract: In one embodiment, the present invention includes a semiconductor device mounted to a first side of a circuit board; and at least one voltage regulator device mounted to a second side of the circuit board, the second side opposite to the first side. Examples of the voltage regulator devices include output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

公开(公告)号：DE10196822T5

公开(公告)日：2004-05-06

申请号：DE10196822

申请日：2001-10-12

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  DISHONGH TERRANCE ,  DUJARI PRATEEK ,  LIAN BIN

IPC: H01R12/57 ,  H01R12/70 ,  H05K3/34 ,  H01R12/36 ,  H01R4/02

Abstract: An enhanced joint thickness lead used for surface mounting electronic devices to a substrate, wherein a portion of the enhanced joint thickness lead that is substantially parallel to the substance. The enhanced joint thickness lead includes an arcuate structure, which provides an enhanced joint thickness for the solder used to connect the lead to the substrate. The enhanced joint thickness of the solder results in a more robust attachment of the electronic device.

公开(公告)号：AU2003261105A1

公开(公告)日：2004-01-23

申请号：AU2003261105

申请日：2003-07-02

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  DISHONGH TERRANCE ,  JACKSON JAMES

IPC: H01L23/433

Abstract: An embodiment of the present invention described and shown in the specification and drawings is a process and a package for facilitating cooling and grounding for a semiconductor die using carbon nanotubes in a thermal interface layer between the die and a thermal management aid. The embodiments that are disclosed have the carbon nanotubes positioned and sized to utilize their high thermal and electrical conductance to facilitate the flow of heat and current to the thermal management aid. One embodiment disclosed has the carbon nanotubes mixed with a paste matrix before being applied. Another disclosed embodiment has the carbon nanotubes grown on the surface of the semiconductor die.

公开(公告)号：AU2003233619A1

公开(公告)日：2003-12-12

申请号：AU2003233619

申请日：2003-05-21

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  ROTH WESTON ,  JACKSON JAMES

IPC: H01L21/60 ,  H01L23/64 ,  H05K1/02 ,  H05K1/14

公开(公告)号：GB2384921A

公开(公告)日：2003-08-06

申请号：GB0310705

申请日：2001-10-12

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  DISHONGH TERRANCE ,  DUJARI PRATEEK ,  LIAN BIN

IPC: H01R12/57 ,  H01R12/70 ,  H05K3/34 ,  H01R13/73

Abstract: An enhanced joint thickness lead used for surface mounting electronic devices to a substrate, wherein a portion of the enhanced joint thickness lead that is substantially parallel to the substance. The enhanced joint thickness lead includes an arcuate structure, which provides an enhanced joint thickness for the solder used to connect the lead to the substrate. The enhanced joint thickness of the solder results in a more robust attachment of the electronic device.

公开(公告)号：AU1164502A

公开(公告)日：2002-05-06

申请号：AU1164502

申请日：2001-10-12

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  DISHONGH TERRANCE ,  DUJARI PRATEEK ,  LIAN BIN

IPC: H01R12/57 ,  H01R12/70 ,  H05K3/34 ,  H01R12/36 ,  H01R4/02

Abstract: An enhanced joint thickness lead used for surface mounting electronic devices to a substrate, wherein a portion of the enhanced joint thickness lead that is substantially parallel to the substance. The enhanced joint thickness lead includes an arcuate structure, which provides an enhanced joint thickness for the solder used to connect the lead to the substrate. The enhanced joint thickness of the solder results in a more robust attachment of the electronic device.

公开(公告)号：BRPI0913484A2

公开(公告)日：2016-08-30

申请号：BRPI0913484

申请日：2009-08-27

Applicant: INTEL CORP

Inventor： GEALER CHARLES E ,  SEARLS DAMION ,  JACKSON JAMES D ,  RAMIREZ MARGARET D ,  THOMAS RAINER E ,  ROTH WESTON C

IPC: H01L23/12 ,  H01L23/48

公开(公告)号：AT552718T

公开(公告)日：2012-04-15

申请号：AT04708986

申请日：2004-02-06

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  RUTTAN THOMAS ,  MANIK JITEENDER

IPC: H05K7/10 ,  H01R12/51 ,  H01R12/57

Abstract: A conventional land grid array (LGA) socket assembly uses the same socket contact in the power delivery area and the signal delivery area. Using low current socket contacts in the power delivery area may create self-heating and limit power delivery from a printed circuit board (PCB) to an IC package mounted in the socket. Embodiments of the present invention are directed to an LGA socket assembly that has a separate power delivery contact, which includes contact pins and contacts pads that are ganged using a cross beam to form a comb-shaped contact. In an alternative embodiment of the present invention, an LGA socket assembly has a shorter channel in the power delivery area than in known LGA socket assemblies. In still another embodiment, an LGA socket assembly has a shorter channel in the power delivery area in the signal delivery area.

公开(公告)号：GB2475658A

公开(公告)日：2011-05-25

申请号：GB201104809

申请日：2009-08-27

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  ROTH WESTON C ,  RAMIREZ MARGARET D ,  JACKSON JAMES D ,  THOMAS RAINER E ,  GEALER CHARLES E

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/12 ,  H05K1/18

Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.

公开(公告)号：DE10196822B4

公开(公告)日：2007-08-30

申请号：DE10196822

申请日：2001-10-12

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  DISHONGH TERRANCE ,  DUJARI PRATEEK ,  LIAN BIN

IPC: H01R4/02 ,  H01R12/57 ,  H01R12/70 ,  H05K3/34

Abstract: An enhanced joint thickness lead used for surface mounting electronic devices to a substrate, wherein a portion of the enhanced joint thickness lead that is substantially parallel to the substance. The enhanced joint thickness lead includes an arcuate structure, which provides an enhanced joint thickness for the solder used to connect the lead to the substrate. The enhanced joint thickness of the solder results in a more robust attachment of the electronic device.