公开(公告)号：JP2012151487A

公开(公告)日：2012-08-09

申请号：JP2012060023

申请日：2012-03-16

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： ROTH WESTON ,  BYRD KEVIN ,  SEARLS DAMION ,  JACKSON JAMES D

IPC: H01L21/60 ,  H05K1/14 ,  H05K3/34

CPC classification number: H05K3/3484 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10719 ,  H05K2201/10992 ,  H05K2203/043 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

Abstract: PROBLEM TO BE SOLVED: To provide a flat solder grid array for a surface mounting component of a printed circuit board.SOLUTION: A standoff contact array is disposed between a mount substrate of a flip-flop package and a board (410). The stand off contact array may be formed by joining flat solder bumps on the mount substrate with flat solder pastes on the board (430). After joining, the standoff contact array is formed by re-flowing the flat solder pastes on the board to the flat solder bumps on the mount substrate (440).

Abstract translation: 要解决的问题：为印刷电路板的表面安装部件提供平坦的焊料栅格阵列。 解决方案：在触发器封装的安装基板和板（410）之间设置间隔接触阵列。 可以通过将安装基板上的扁平焊料凸块与板上的平坦焊膏（430）接合来形成支座接触阵列。 在接合之后，通过将板上的扁平焊膏重新流动到安装基板（440）上的扁平焊料凸块来形成间隔接触阵列。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2009302539A

公开(公告)日：2009-12-24

申请号：JP2009140269

申请日：2009-06-11

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： ROTH WESTON ,  BYRD KEVIN ,  SEARLS DAMION ,  JACKSON JAMES D

IPC: H01L21/60 ,  H01L23/12 ,  H05K3/34

CPC classification number: H05K3/3484 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10719 ,  H05K2201/10992 ,  H05K2203/043 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

Abstract: PROBLEM TO BE SOLVED: To provide a low profile solder grid array for components surface-mounted on a printed circuit board.
SOLUTION: A standoff contact array is arranged between a mounting substrate of a flip-chip package and a board. The standoff contact array can be formed by mating a low-profile solder bump on the mounting substrate with a low-profile solder paste on the board. Thereafter, the standoff contact array is formed by reflowing the low-profile solder paste on the board against the low-profile solder bump on the mounting substrate.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为表面安装在印刷电路板上的部件提供一种薄型焊料阵列。 解决方案：在倒装芯片封装的安装基板和板之间布置有间隔触点阵列。 间隔接触阵列可以通过将安装基板上的低轮廓焊料凸块与板上的低轮廓焊膏相配合来形成。 此后，通过将板上的低轮廓焊膏回流到安装基板上的低轮廓焊料凸块上来形成间隔接触阵列。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：WO2010027890A2

公开(公告)日：2010-03-11

申请号：PCT/US2009055133

申请日：2009-08-27

Applicant: INTEL CORP ,  SEARLS DAMION ,  ROTH WESTON C ,  RAMIREZ MARGARET D ,  JACKSON JAMES D ,  THOMAS RAINER E ,  GEALER CHARLES E

Inventor： SEARLS DAMION ,  ROTH WESTON C ,  RAMIREZ MARGARET D ,  JACKSON JAMES D ,  THOMAS RAINER E ,  GEALER CHARLES E

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H05K1/181 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K3/284 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.

Abstract translation: 公开了包括直接附接到主板的集成电路（IC）裸片的系统级组件的实施例。 直接连接到主板或其他电路板的IC管芯可以被称为直接芯片连接（DCA）管芯。 封装设置在DCA管芯的至少一部分上并与主板耦合。 该封装包括设置在衬底上的一个或多个其他IC管芯。 描述并要求保护其他实施例。

公开(公告)号：WO0235655A3

公开(公告)日：2002-08-29

申请号：PCT/US0131815

申请日：2001-10-12

Applicant: INTEL CORP ,  SEARLS DAMION ,  DISHONGH TERRANCE ,  DUJARI PRATEEK ,  LIAN BIN

Inventor： SEARLS DAMION ,  DISHONGH TERRANCE ,  DUJARI PRATEEK ,  LIAN BIN

IPC: H01R12/57 ,  H01R12/70 ,  H05K3/34 ,  H01R12/36 ,  H01R4/02

CPC classification number: H01R12/57 ,  H01R12/7011 ,  H01R12/707 ,  H05K3/3426 ,  Y02P70/613

Abstract: An enhanced joint thickness lead used for surface mounting electronic devices to a substrate, wherein a portion of the enhanced joint thickness lead that is substantially parallel to the substance. The enhanced joint thickness lead includes an arcuate structure, which provides an enhanced joint thickness for the solder used to connect the lead to the substrate. The enhanced joint thickness of the solder results in a more robust attachment of the electronic device.

Abstract translation: 用于将电子器件表面安装到基底的增强的接合厚度引线，其中增强的接合厚度引线的一部分基本上平行于物质。 增强的接头厚度引线包括弓形结构，其为用于将引线连接到衬底的焊料提供增强的接合厚度。 焊料的增强的接合厚度导致电子器件的更牢固的附着。

公开(公告)号：GB2475658B

公开(公告)日：2012-11-28

申请号：GB201104809

申请日：2009-08-27

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  ROTH WESTON C ,  RAMIREZ MARGARET D ,  JACKSON JAMES D ,  THOMAS RAINER E ,  GEALER CHARLES E

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/12 ,  H05K1/18

Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.

公开(公告)号：GB2384921B

公开(公告)日：2004-07-21

申请号：GB0310705

申请日：2001-10-12

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  DISHONGH TERRANCE ,  DUJARI PRATEEK ,  LIAN BIN

IPC: H01R12/57 ,  H01R12/70 ,  H05K3/34 ,  H01R13/73

Abstract: An enhanced joint thickness lead used for surface mounting electronic devices to a substrate, wherein a portion of the enhanced joint thickness lead that is substantially parallel to the substance. The enhanced joint thickness lead includes an arcuate structure, which provides an enhanced joint thickness for the solder used to connect the lead to the substrate. The enhanced joint thickness of the solder results in a more robust attachment of the electronic device.

公开(公告)号：DE60135241D1

公开(公告)日：2008-09-18

申请号：DE60135241

申请日：2001-10-12

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  DISHONGH TERRANCE ,  DUJARI PRATEEK ,  LIAN BIN

IPC: H01R4/02 ,  H01R12/57 ,  H01R12/70 ,  H05K3/34

Abstract: An enhanced joint thickness lead used for surface mounting electronic devices to a substrate, wherein a portion of the enhanced joint thickness lead that is substantially parallel to the substance. The enhanced joint thickness lead includes an arcuate structure, which provides an enhanced joint thickness for the solder used to connect the lead to the substrate. The enhanced joint thickness of the solder results in a more robust attachment of the electronic device.

公开(公告)号：AT373409T

公开(公告)日：2007-09-15

申请号：AT01920931

申请日：2001-04-03

Applicant: INTEL CORP

Inventor： DISHONGH TERRANCE ,  SEARLS DAMION ,  LIAN BIN ,  DUJARI PRATEEK

IPC: F16F15/02 ,  H05K1/02 ,  F16F15/00 ,  G05D19/02 ,  H05K1/18

Abstract: Piezoelectric wafers are affixed to a circuit card to control displacement of the circuit card when vibrated. A trigger wafer located at an anti-node of the dominant mode shape produces a voltage as a function of modal displacement. A control system responsive to the trigger wafer produces voltages that are applied to flex wafers at a different anti-node of the dominant mode shape. The flex wafers expand and contract in a manner that reduces the modal displacement of the circuit card. Multiple flex wafers can exist, affixed to the circuit card substantially opposite each other, or a single flex wafer can exist with a single trigger wafer. The trigger wafer can be located substantially opposite the flex wafer or can be located elsewhere on the circuit card.

公开(公告)号：AU2003230702A1

公开(公告)日：2003-10-13

申请号：AU2003230702

申请日：2003-03-19

Applicant: INTEL CORP

Inventor： SEARLS DAMION ,  DUJARI PRATEEK ,  LIAN BIN

IPC: H01L21/02 ,  H01L21/04 ,  H01L21/768 ,  H01L23/373 ,  H01L23/48 ,  H01L23/64

Abstract: A semiconductor substrate with integrated circuit devices on its front side and a high thermal conductivity layer such as diamond on its back side, with components such as capacitors embedded in the high thermal conductivity layer and coupled to the front side integrated circuits with vias through the substrate.

公开(公告)号：DE60130450T2

公开(公告)日：2008-05-29

申请号：DE60130450

申请日：2001-04-03

Applicant: INTEL CORP

Inventor： DISHONGH TERRANCE ,  SEARLS DAMION ,  LIAN BIN ,  DUJARI PRATEEK

IPC: F16F15/02 ,  H05K1/02 ,  F16F15/00 ,  G05D19/02 ,  H05K1/18

Abstract: Piezoelectric wafers are affixed to a circuit card to control displacement of the circuit card when vibrated. A trigger wafer located at an anti-node of the dominant mode shape produces a voltage as a function of modal displacement. A control system responsive to the trigger wafer produces voltages that are applied to flex wafers at a different anti-node of the dominant mode shape. The flex wafers expand and contract in a manner that reduces the modal displacement of the circuit card. Multiple flex wafers can exist, affixed to the circuit card substantially opposite each other, or a single flex wafer can exist with a single trigger wafer. The trigger wafer can be located substantially opposite the flex wafer or can be located elsewhere on the circuit card.