公开(公告)号：US10923443B2

公开(公告)日：2021-02-16

申请号：US16369708

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC: H01L23/495 ,  H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US20200251467A1

公开(公告)日：2020-08-06

申请号：US16855376

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Rahul Jain ,  Seo Young Kim ,  Kyu Oh Lee ,  Ji Yong Park ,  Sai Vadlamani ,  Junnan Zhao

IPC: H01L27/07 ,  H01L49/02 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

公开(公告)号：US20200066543A1

公开(公告)日：2020-02-27

申请号：US16113109

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Sai Vadlamani ,  Junnan Zhao ,  Ji Yong Park ,  Kyu Oh Lee ,  Cheng Xu

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

公开(公告)号：US20200006210A1

公开(公告)日：2020-01-02

申请号：US16019807

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park

IPC: H01L23/498 ,  H01L21/48

Abstract: A chip package that includes a die coupled to a package substrate. The substrate includes a first ground layer and a dielectric material engaging the first ground layer. A solder resist layer engages the dielectric material and a routing layer is disposed at least partially within the solder resist layer. A second ground layer engages the solder resist layer.

公开(公告)号：US20190206780A1

公开(公告)日：2019-07-04

申请号：US15857238

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Prithwish Chatterjee ,  Junnan Zhao ,  Sai Vadlamani ,  Ying Wang ,  Rahul Jain ,  Andrew J. Brown ,  Lauren A. Link ,  Cheng Xu ,  Sheng C. Li

IPC: H01L23/498 ,  H01F27/28 ,  H01L21/48 ,  H01F41/04 ,  H01L25/16

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49816

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

公开(公告)号：US09820386B2

公开(公告)日：2017-11-14

申请号：US15074064

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Rahul Jain ,  Robert Alan May ,  Sheng Li ,  Sri Ranga Sai Boyapati

IPC: H05K3/00 ,  H05K1/09 ,  H05K1/03

CPC classification number: H05K3/0041 ,  H05K1/0313 ,  H05K1/09 ,  H05K3/0055 ,  H05K3/3452 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/0562 ,  H05K2203/0588 ,  H05K2203/095

Abstract: A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.

公开(公告)号：US12154715B2

公开(公告)日：2024-11-26

申请号：US17873518

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01F27/28 ,  H01F27/02 ,  H01F27/24 ,  H05K1/18

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US12009271B2

公开(公告)日：2024-06-11

申请号：US16511360

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Edvin Cetegen ,  Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Nicholas Neal ,  Sergio Chan Arguedas ,  Vipul Mehta

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US11737208B2

公开(公告)日：2023-08-22

申请号：US16268813

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L23/498

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.

公开(公告)号：US11652071B2

公开(公告)日：2023-05-16

申请号：US17158634

申请日：2021-01-26

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC: H01L23/495 ,  H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

CPC classification number: H01L23/642 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L28/40

Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.