公开(公告)号：US20220352029A1

公开(公告)日：2022-11-03

申请号：US17863292

申请日：2022-07-12

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Christopher J. Jezewski ,  Willy Rachmady ,  Rishabh Mehandru ,  Gilbert Dewey ,  Anh Phan

IPC: H01L21/8234 ,  H01L29/78

Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.

公开(公告)号：US11430868B2

公开(公告)日：2022-08-30

申请号：US16020361

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani ,  Stephen M. Cea

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66 ,  H01L29/20 ,  H01L29/161 ,  H01L29/16

Abstract: Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.

公开(公告)号：US11367722B2

公开(公告)日：2022-06-21

申请号：US16138356

申请日：2018-09-21

Applicant: INTEL CORPORATION

Inventor： Aaron Lilak ,  Stephen Cea ,  Gilbert Dewey ,  Willy Rachmady ,  Roza Kotlyar ,  Rishabh Mehandru ,  Sean Ma ,  Ehren Mannebach ,  Anh Phan ,  Cheng-Ying Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/16

Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.

公开(公告)号：US11342432B2

公开(公告)日：2022-05-24

申请号：US16833184

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Cory Weber ,  Willy Rachmady ,  Varun Mishra

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US11276780B2

公开(公告)日：2022-03-15

申请号：US16024724

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Tahir Ghani ,  Stephen Cea

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

公开(公告)号：US11257929B2

公开(公告)日：2022-02-22

申请号：US15770463

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak

IPC: H01L27/00 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

公开(公告)号：US11239236B2

公开(公告)日：2022-02-01

申请号：US16827566

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Ehren Mannebach ,  Patrick Morrow ,  Willy Rachmady

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/10

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

公开(公告)号：US11139241B2

公开(公告)日：2021-10-05

申请号：US16348105

申请日：2016-12-07

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC: H01L23/528 ,  H01L27/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/772 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US11049861B2

公开(公告)日：2021-06-29

申请号：US15747692

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Morrow ,  Rishabh Mehandru ,  Donald W. Nelson ,  Stephen M. Cea

IPC: H01L27/108

Abstract: Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.

公开(公告)号：US20210111115A1

公开(公告)日：2021-04-15

申请号：US17127863

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru

IPC: H01L23/528 ,  H01L29/78 ,  G06F30/394 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/772 ,  G06F30/392

Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.