公开(公告)号：AU2003223595A1

公开(公告)日：2003-11-03

申请号：AU2003223595

申请日：2003-04-15

Applicant: INTERDIGITAL TECH CORP

Inventor： BASS DAVID S ,  CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  LEVI ALAN M ,  DESAI BINISH ,  HEPLER EDWARD L ,  STARSINIC MICHAEL F

IPC: H04J1/00 ,  H04B1/40 ,  H04B1/707 ,  H04B7/26 ,  H04J3/00 ,  H04J4/00 ,  H04L1/00 ,  H04L1/08 ,  H04L12/56 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00 ,  H04W88/02

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

公开(公告)号：CA2482616A1

公开(公告)日：2003-10-30

申请号：CA2482616

申请日：2003-04-15

Applicant: INTERDIGITAL TECH CORP

Inventor： BASS DAVID S ,  CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  LEVI ALAN M ,  DESAI BINISH ,  HEPLER EDWARD L ,  STARSINIC MICHAEL F

IPC: H04J1/00 ,  H04B1/40 ,  H04B1/707 ,  H04B7/26 ,  H04J3/00 ,  H04J4/00 ,  H04L1/00 ,  H04L1/08 ,  H04L12/56 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00 ,  H04W88/02

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (303, 307), a composite channel processing block (305, 309) and a chip rate processing block (301, 311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of paramete rs is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

公开(公告)号：ES2276058T3

公开(公告)日：2007-06-16

申请号：ES03719734

申请日：2003-04-15

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  STARSINIC MICHAEL F ,  BASS DAVID S ,  DESAI BINISH ,  LEVI ALAN M ,  MCCLELLAN GEORGE W

IPC: H04J1/00 ,  H04J4/00 ,  H04B1/40 ,  H04B1/707 ,  H04B7/26 ,  H04J3/00 ,  H04L1/00 ,  H04L1/08 ,  H04L12/56 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00 ,  H04W88/02

Abstract: Un método para el procesado compuesto de canales de transporte en una capa física, siendo dicho método para uso para procesar comunicaciones inalámbricas, comprendiendo el método: proporcionar una pluralidad de bloques de procesado interconectados por un bus de sistema (302), incluyendo la pluralidad de bloques interconectados un bloque de procesado de canal de transporte (305, 307) para procesar los datos sobre una base de canal de transporte, un bloque de procesado de canal compuesto (303, 309) para procesar los datos sobre una base de canales de transporte compuestos y un bloque de procesador de régimen de chips (301, 311) para procesar los datos asociados con una interfaz inalámbrica, siendo dos al menos de los bloques de procesado capaces de procesar datos para una pluralidad de formatos inalámbricos; programar un primer conjunto de parámetros en dicha pluralidad de bloques de procesado interconectados, definiendo dicho primer conjunto de parámetros un formato inalámbrico particular; yoperar los bloques de procesado interconectados para procesar los datos en el formato inalámbrico particular definido por el primer conjunto de parámetros.

公开(公告)号：AT350822T

公开(公告)日：2007-01-15

申请号：AT03719734

申请日：2003-04-15

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  STARSINIC MICHAEL F ,  BASS DAVID S ,  DESAI BINISH ,  LEVI ALAN M ,  MCCLELLAN GEORGE W ,  CASTOR DOUGLAS R

IPC: H04J1/00 ,  H04B1/40 ,  H04B1/707 ,  H04B7/26 ,  H04J3/00 ,  H04J4/00 ,  H04L1/00 ,  H04L1/08 ,  H04L12/56 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00 ,  H04W88/02

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

公开(公告)号：NO20044923L

公开(公告)日：2005-01-05

申请号：NO20044923

申请日：2004-11-11

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  STARSINIC MICHAEL F ,  LEVI ALAN M ,  BASS DAVID S ,  DESAI BINISH

IPC: H04B1/40 ,  H04B1/707 ,  H04J1/00 ,  H04B7/26 ,  H04J3/00 ,  H04J4/00 ,  H04L1/00 ,  H04L1/08 ,  H04L12/56 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00 ,  H04W88/02 ,  G06F13/00

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

公开(公告)号：BR0212645A

公开(公告)日：2004-08-24

申请号：BR0212645

申请日：2002-04-15

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  STARSINIC MICHAEL F

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/39 ,  H03M13/45 ,  G06N5/04

Abstract: The application relates to sliding-window maximum a posteriori MAP decoding. In a MAP decoder, a method for determining binary states of received signals comprises receiving data bits, each bit being accompanied by at least one parity bit, providing each received data bit and parity bit with an address (16a) of a calculated extrinsic value (14a) and associated intrinsic data and storing the data bits, the parity bits and the extrinsic value address in a first memory (12).

公开(公告)号：NO20041357L

公开(公告)日：2004-04-01

申请号：NO20041357

申请日：2004-04-01

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  STARSINIC MICHAEL F

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/39 ,  H03M13/45 ,  G06N5/04

Abstract: The application relates to sliding-window maximum a posteriori MAP decoding. In a MAP decoder, a method for determining binary states of received signals comprises receiving data bits, each bit being accompanied by at least one parity bit, providing each received data bit and parity bit with an address (16a) of a calculated extrinsic value (14a) and associated intrinsic data and storing the data bits, the parity bits and the extrinsic value address in a first memory (12).