公开(公告)号：CA2517221A1

公开(公告)日：2004-09-16

申请号：CA2517221

申请日：2004-03-01

Applicant: INTERDIGITAL TECH CORP

Inventor： NASUTI TONINO ,  BECKER PETER EDWARD ,  HAIM JOHN W ,  DIFAZIO ROBERT A ,  BUCHERT RYAN SAMUEL ,  TIMMERMAN CHAYIL S ,  SUPPLEE STEPHAN SHANE

IPC: H04B1/707 ,  H04B7/216

Abstract: Multi-user detection (MUD) performance is optimized to eliminate redundant use of power during processing. An overbuilt A-matrix, i.e., a system response matrix, is provided. The overbuilt A-matrix uses all possible codes, e.g., all codes identified in a candidate code list (CCL) provided by blind code detection (BCD). The overbuilt A-matrix is passed to the MUD which extracts only those rows or columns required for codes that have actually been received, thus eliminating the need to recompute whitening matched filter (WMF) outputs that do not correspond to the actually received code.

公开(公告)号：DE60331088D1

公开(公告)日：2010-03-11

申请号：DE60331088

申请日：2003-09-24

Applicant: INTERDIGITAL TECH CORP

Inventor： BUCHERT RYAN S ,  TIMMERMAN CHAYIL S ,  SUPPLEE STEPHAN SHANE

IPC: G06F7/38 ,  G06F5/01 ,  G06F7/00 ,  G06F7/52 ,  G06F17/14 ,  G06F17/16 ,  G06K20060101

Abstract: A method and system for performing many different types if algorithms utilizes a single mathematical engine (30) such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical engine includes a selectively controlled parallel output register (33), at least one selectively controlled memory (31), and a plurality of processing elements (40). The output register, the memory and the processing elements are selectively controlled depending upon the algorithm to be performed.

公开(公告)号：DE602004015426D1

公开(公告)日：2008-09-11

申请号：DE602004015426

申请日：2004-03-01

Applicant: INTERDIGITAL TECH CORP

Inventor： SUPPLEE STEPHAN SHANE ,  TIMMERMAN CHAYIL S ,  BUCHERT RYAN SAMUEL ,  BECKER PETER EDWARD ,  NASUTI TONINO ,  DIFAZIO ROBERT A ,  HAIM JOHN W

IPC: H04B7/216 ,  H04B1/707

Abstract: Multi-user detection (MUD) performance is optimized to eliminate redundant use of power during processing. An overbuilt A-matrix, i.e., a system response matrix, is provided. The overbuilt A-matrix uses all possible codes, e.g., all codes identified in a candidate code list (CCL) provided by blind code detection (BCD). The overbuilt A-matrix is passed to the MUD which extracts only those rows or columns required for codes that have actually been received, thus eliminating the need to recompute whitening matched filter (WMF) outputs that do not correspond to the actually received code.

公开(公告)号：NO20051806L

公开(公告)日：2005-06-08

申请号：NO20051806

申请日：2005-04-13

Applicant: INTERDIGITAL TECH CORP

Inventor： SUPPLEE STEPHAN SHANE ,  BUCHERT RYAN SAMUEL ,  TIMMERMAN CHAYIL

IPC: G06F5/01 ,  G06F7/00 ,  G06F7/38 ,  G06F7/52 ,  G06F17/16 ,  G06K20060101

Abstract: A method and system for performing many different types if algorithms utilizes a single mathematical engine (30) such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical engine includes a selectively controlled parallel output register (33), at least one selectively controlled memory (31), and a plurality of processing elements (40). The output register, the memory and the processing elements are selectively controlled depending upon the algorithm to be performed.

公开(公告)号：AU2003270874A1

公开(公告)日：2004-04-19

申请号：AU2003270874

申请日：2003-09-24

Applicant: INTERDIGITAL TECH CORP

Inventor： BUCHERT RYAN S ,  TIMMERMAN CHAYIL S ,  SUPPLEE STEPHAN SHANE

IPC: G06F5/01 ,  G06F7/00 ,  G06F7/38 ,  G06F7/52 ,  G06F17/16 ,  G06K20060101

Abstract: A method and system for performing many different types if algorithms utilizes a single mathematical engine (30) such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical engine includes a selectively controlled parallel output register (33), at least one selectively controlled memory (31), and a plurality of processing elements (40). The output register, the memory and the processing elements are selectively controlled depending upon the algorithm to be performed.

公开(公告)号：CA2466684A1

公开(公告)日：2003-05-22

申请号：CA2466684

申请日：2002-11-13

Applicant: INTERDIGITAL TECH CORP

Inventor： SUPPLEE STEPHAN SHANE ,  BECKER PETER E

IPC: G06F17/16 ,  G06F17/12 ,  H04B1/707 ,  H04B7/155 ,  H04B15/00 ,  H04K1/00 ,  H04L27/30

Abstract: Processing elements (54-54N) are utilized for solving linear systems. One embodiment (Fig. 3B) projects matrix elements along a diagonal of the matrix onto scalar processing elements to determine a Cholesky factor. Another embodiment uses a two-dimensional scalar array to determine a Cholesky facto r. For matrices having a limited bandwidth, the processors (54-54N) may be used to reduce the number of processors used.