公开(公告)号：US20180331003A1

公开(公告)日：2018-11-15

申请号：US15776755

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Adel A. ELSHERBINI ,  Mihir K. ROY ,  Aleksandar ALEKSOV ,  Yidnekachew S. MEKONNEN ,  Javier SOTO GONZALEZ ,  Feras EID ,  Suddhasattwa NAD ,  Meizi JIAO

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/12 ,  H01L21/486 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US20180288868A1

公开(公告)日：2018-10-04

申请号：US15997644

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Matthew MANUSHAROW ,  Krishna BHARATH ,  Zhichao ZHANG ,  Yidnekachew S. MEKONNEN ,  Aleksandar ALEKSOV ,  Henning BRAUNISCH ,  Feras EID ,  Javier SOTO

IPC: H05K1/02 ,  H01P3/08 ,  H01P3/02

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20180019213A1

公开(公告)日：2018-01-18

申请号：US15546958

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Rajendra C. DIAS ,  Tatyana N. ANDRYUSHCHENKO ,  Mauro J. KOBRINSKY ,  Aleksandar ALEKSOV ,  David W. STAINES

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

Abstract: Embodiments of the invention include a microelectronic device and methods for forming a microelectronic device. In an embodiment, the microelectronic device includes a semiconductor die that has one or more die contacts that are each electrically coupled to a contact pad by a conductive trace. The semiconductor die may have a first elastic modulus. The microelectronic device may also include an encapsulation layer over the semiconductor die and the conductive trace. The encapsulation layer may have a second elastic modulus that is less than the first elastic modulus. The microelectronic device may also include a first strain redistribution layer within the encapsulation layer. The first strain redistribution layer may have a footprint that covers the semiconductor die and a portion of the conductive traces. The strain redistribution layer may have a third elastic modulus that is less than the first elastic modulus and greater than the second elastic modulus.

公开(公告)号：US20250107112A1

公开(公告)日：2025-03-27

申请号：US18371294

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas PIETAMBARAM ,  Mohammad Mamunur RAHMAN ,  Sashi Shekhar KANDANUR ,  Aleksandar ALEKSOV ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI

IPC: H01L23/48 ,  H01L23/498

Abstract: Coaxial magnetic inductor structures useful for semiconductor packaging applications are provided. The coaxial magnetic inductors can be located in semiconductor package cores and the semiconductor package cores can be, for example, comprised of an amorphous solid glass material. Methods of manufacturing a coaxial magnetic inductors in a package substrate core are also provided.

公开(公告)号：US20250079300A1

公开(公告)日：2025-03-06

申请号：US18240318

申请日：2023-08-30

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Neelam PRABHU GAUNKAR ,  Henning BRAUNISCH ,  Wenhao LI ,  Feras EID ,  Georgios C. DOGIAMIS

IPC: H01L23/522 ,  H01F1/03 ,  H01F41/16

Abstract: Magnetic inductors for microelectronics packages are provided. Magnetic inductive structures include a magnetic region, a magnetic region base region, and a conductive region that forms a channel within the magnetic region. The magnetic region has a different chemical composition than the base region. Additional structures are provided in which the magnetic region is recessed into a package substrate core. Further inductor structures are provided in which the conductive region includes through-core vias and the conductive region at least partially encircles a portion of a package substrate core. Additionally, methods of manufacture are provided for semiconductor packages that include magnetic inductors.

公开(公告)号：US20250070083A1

公开(公告)日：2025-02-27

申请号：US18942054

申请日：2024-11-08

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20240030150A1

公开(公告)日：2024-01-25

申请号：US18374595

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Johanna M. SWAN

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L23/498 ,  H01L23/367 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L25/0652 ,  H01L23/5389 ,  H01L25/16 ,  H01L23/49816 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/13 ,  H01L24/17 ,  H01L2225/06589 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2224/32245 ,  H01L24/32 ,  H01L24/73 ,  H01L2225/06541 ,  H01L2225/06513

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.

公开(公告)号：US20230197592A1

公开(公告)日：2023-06-22

申请号：US17553189

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Brandon RAWLINGS ,  Aleksandar ALEKSOV ,  Andrew P. COLLINS ,  Georgios C. DOGIAMIS ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/15 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/181

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first buildup layer is over the first surface of the core, and a second buildup layer is under the second surface of the core. In an embodiment, the electronic package further comprises a via through the core between the first surface of the core and the second surface of the core, and a plane into the first surface of the core, where a width of the plane is greater than a width of the via.

公开(公告)号：US20230093438A1

公开(公告)日：2023-03-23

申请号：US17481266

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Bai NIE ,  Tarek A. IBRAHIM ,  Ankur AGRAWAL ,  Sandeep GAAN ,  Ravindranath V. MAHAJAN ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H04B10/70 ,  G02B6/124 ,  G02B6/13

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises a mold material. In an embodiment, a first photonics integrated circuit (PIC) is within the second layer. In an embodiment, a second PIC is within the second layer, and a waveguide is in the first layer. In an embodiment, the waveguide optically couples the first PIC to the second PIC.

公开(公告)号：US20230015619A1

公开(公告)日：2023-01-19

申请号：US17952080

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Kristof DARMAWAIKARTA ,  Robert MAY ,  Sashi KANDANUR ,  Sri Ranga Sai BOYAPATI ,  Srinivas PIETAMBARAM ,  Steve CHO ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Ravindranadh ELURI ,  Hiroki TANAKA ,  Aleksandar ALEKSOV ,  Dilan SENEVIRATNE

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).