公开(公告)号：US11888034B2

公开(公告)日：2024-01-30

申请号：US16435358

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ashish Agarwal ,  Urusa Alaan ,  Christopher Jezewski ,  Kevin Lin ,  Carl Naylor

IPC: H01L29/26 ,  H01L29/51 ,  H01L29/16 ,  H01L27/092

CPC classification number: H01L29/26 ,  H01L27/092 ,  H01L29/16 ,  H01L29/517

Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.

公开(公告)号：US11742346B2

公开(公告)日：2023-08-29

申请号：US16024058

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Christopher Jezewski ,  Ehren Mannebach ,  Rishabh Mehandru ,  Patrick Morrow ,  Anand S. Murthy ,  Anh Phan ,  Willy Rachmady

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/48 ,  H01L23/522 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/822 ,  H01L23/00

CPC classification number: H01L27/0886 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L27/0924 ,  H01L24/94 ,  H01L2224/29188 ,  H01L2224/32145

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

公开(公告)号：US20220139775A1

公开(公告)日：2022-05-05

申请号：US17087521

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Christopher Jezewski

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Integrated circuit interconnect structures including an interconnect metallization feature with a barrier material comprising a metal and a chalcogen. Introduction of the chalcogen may improve diffusion barrier properties at a given barrier material layer thickness with increasing the barrier layer thickness. A barrier material, such as TaN, may be deposited at minimal thickness, and doped with a chalcogen before or after one or more fill materials are deposited over the barrier material. During thermal processing mobile chalcogen impurities may collect within regions within the barrier material to high enough concentrations for at least a portion of the barrier material to be converted into a metal chalcogenide layer. The metal chalcogenide layer may have greater crystallinity than a remainder of the barrier layer.

公开(公告)号：US20220059702A1

公开(公告)日：2022-02-24

申请号：US17517583

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US11018075B2

公开(公告)日：2021-05-25

申请号：US16221815

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L27/12 ,  H01L23/40 ,  H01L21/822 ,  H01L23/532 ,  H01L21/70

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US20200185532A1

公开(公告)日：2020-06-11

申请号：US16214706

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Kevin Lin ,  Abhishek Sharma ,  Carl Naylor ,  Urusa Alaan ,  Christopher Jezewski ,  Ashish Agrawal

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/24 ,  H01L29/417

Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.

公开(公告)号：US10201081B2

公开(公告)日：2019-02-05

申请号：US15676519

申请日：2017-08-14

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ravi Pillarisetty ,  Brian Doyle

IPC: H01L23/52 ,  H05K1/03 ,  D03D1/00 ,  D03D11/02 ,  D03D15/00 ,  H05K3/00 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K1/18 ,  H05K3/28

Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.

公开(公告)号：US09165824B2

公开(公告)日：2015-10-20

申请号：US14039893

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Hui Jae Yoo ,  Christopher Jezewski ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.

Abstract translation: 包括全覆层互连的金属化层和形成完全包层的互连的方法。 在电介质层中形成开口，其中介电层具有表面，并且开口包括壁和底部。 扩散阻挡层和粘合层沉积在介电层上。 互连材料沉积在介电层上并回流到形成互连的开口中。 在互连上沉积粘合覆盖层和扩散阻挡覆盖层。 互连被粘合层和粘合覆盖层包围，粘合层和粘合覆盖层被扩散阻挡层和扩散覆盖层包围。

公开(公告)号：US12107170B2

公开(公告)日：2024-10-01

申请号：US17517583

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78609 ,  H01L27/1207 ,  H01L29/66969 ,  H01L29/7869

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US20240006506A1

公开(公告)日：2024-01-04

申请号：US17856979

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Jack T. Kavalieros ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/458 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/401

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Phosphide and arsenide metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting the amount of contact metal that diffuses into source/drain regions.