公开(公告)号：US20230093258A1

公开(公告)日：2023-03-23

申请号：US17482830

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Haobo CHEN ,  Leonel ARANA

IPC: H01L23/498 ,  H01L23/15 ,  H01L21/48

Abstract: Embodiments include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first substrate, and a second substrate coupled to the first substrate. In an embodiment, the second substrate comprises a core, and the core comprises an organic material. In an embodiment, a third substrate is coupled to the second substrate, and the third substrate comprises a glass layer.

公开(公告)号：US20220285278A1

公开(公告)日：2022-09-08

申请号：US17752717

申请日：2022-05-24

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Oscar OJEDA ,  Arnab ROY ,  Vahidreza PARICHEHREH ,  Leonel R. ARANA ,  Chung Kwang TAN ,  Robert A. MAY

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20240339381A1

公开(公告)日：2024-10-10

申请号：US18130582

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Hiroki TANAKA ,  Veronica STRONG ,  Henning BRAUNISCH ,  Haobo CHEN ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Brandon C. MARIN

IPC: H01L23/482 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/4821 ,  H01L21/76831 ,  H01L23/49827 ,  H01L23/49866 ,  H01L21/30604 ,  H05K2201/09218

Abstract: Embodiments disclosed herein include an interposer. In an embodiment, the interposer comprises a substrate, where the substrate comprises a glass layer. In an embodiment, a trace is on the substrate, where the trace has a bottom surface, sidewall surfaces, and a top surface. In an embodiment, the sidewall surfaces and the top surface are exposed to air. In an embodiment, a trench into the substrate is adjacent to at least one sidewall surface of the trace.

公开(公告)号：US20240071935A1

公开(公告)日：2024-02-29

申请号：US17895965

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08225 ,  H01L2224/80894 ,  H01L2224/80895

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate, where the first substrate comprises glass, and a second substrate over the first substrate, where the second substrate comprises glass. In an embodiment, electrically conductive routing is provided in the second substrate. In an embodiment, a first die is over the second substrate, and a second die is over the second substrate. In an embodiment, the electrically conductive routing electrically couples the first die to the second die.

公开(公告)号：US20240071848A1

公开(公告)日：2024-02-29

申请号：US17895916

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Bai NIE ,  Gang DUAN ,  Kyle ARRINGTON ,  Ziyin LIN ,  Hongxia FENG ,  Yiqun BAI ,  Xiaoying GUO ,  Dingying David XU ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.

公开(公告)号：US20240063203A1

公开(公告)日：2024-02-22

申请号：US17889962

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Navneet SINGH ,  Sushil PADMANABHAN ,  Samarth ALVA

IPC: H01L25/18 ,  H01L23/15 ,  H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/481 ,  H01L23/5384 ,  H01L21/486 ,  H01L21/4857 ,  H01L25/50 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass, and buildup layers over the first substrate. In an embodiment, a first die is over the buildup layers, a second die is over the buildup layers and adjacent to the first die, and where conductive routing in the buildup layers electrically couples the first die to the second die.

公开(公告)号：US20240063127A1

公开(公告)日：2024-02-22

申请号：US17889238

申请日：2022-08-16

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/13 ,  H01L23/15 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/13 ,  H01L23/15 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/152 ,  H01L2924/15788 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate with a cavity, where the first substrate comprises glass. In an embodiment, a second substrate is in the cavity. In an embodiment, a bond film covers a bottom of the second substrate and extends up sidewalls of the second substrate.

公开(公告)号：US20230207503A1

公开(公告)日：2023-06-29

申请号：US17561824

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Bainye Francoise ANGOUA ,  Dilan SENEVIRATNE ,  Whitney M. BRYKS ,  Jeremy D. ECTON

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/34 ,  H01L2224/73265 ,  H01L2924/186 ,  H01L2924/01029

Abstract: A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate. The metallic contact has a contact surface to make electrical contact with a trace through a dielectric layer over the semiconductor circuit substrate and the metallic contact. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The metallic contact includes a vertical lip extending vertically into the dielectric layer above the contact surface.

公开(公告)号：US20230137877A1

公开(公告)日：2023-05-04

申请号：US17517152

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Omkar KARHADE ,  Malavarayan SANKARASUBRAMANIAN ,  Dingying XU ,  Gang DUAN ,  Bai NIE ,  Xiaoying GUO ,  Kristof DARMAWIKARTA ,  Hongxia FENG ,  Srinivas PIETAMBARAM ,  Jeremy D. ECTON

IPC: H01L23/00 ,  H01L25/065

Abstract: No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

公开(公告)号：US20230087810A1

公开(公告)日：2023-03-23

申请号：US17482852

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD ,  Oscar OJEDA ,  Bai NIE ,  Brandon C. MARIN ,  Gang DUAN ,  Jacob VEHONSKY ,  Onur OZKAN ,  Nicholas S. HAEHN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.