公开(公告)号：US20220093316A1

公开(公告)日：2022-03-24

申请号：US17029870

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC: H01F27/28 ,  H01L23/64 ,  H01F41/32 ,  H01L23/498

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US20210273036A1

公开(公告)日：2021-09-02

申请号：US16804317

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tarek Ibrahim ,  Prithwish Chatterjee ,  Haifa Hariri ,  Yikang Deng ,  Sheng C. Li ,  Srinivas Pietambaram

IPC: H01L49/02 ,  H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.

公开(公告)号：US12272484B2

公开(公告)日：2025-04-08

申请号：US17192187

申请日：2021-03-04

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Pooya Tadayon ,  Kristof Darmawikarta ,  Tarek Ibrahim ,  Prithwish Chatterjee

IPC: H01F27/28 ,  H01F1/04 ,  H01F27/40 ,  H05K1/16

Abstract: An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

公开(公告)号：US12033930B2

公开(公告)日：2024-07-09

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/485 ,  H01L23/49827

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US20240222301A1

公开(公告)日：2024-07-04

申请号：US18147497

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Srinivas Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Sairam Agraharam ,  Ashay Dani ,  Eric J. M. Moret ,  Tarek Ibrahim

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L2224/10122 ,  H01L2224/11011 ,  H01L2924/143 ,  H01L2924/186

Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.

公开(公告)号：US20240222283A1

公开(公告)日：2024-07-04

申请号：US18147487

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Bohan Shan ,  Bai Nie ,  Xiaoxuan Sun ,  Holly Sawyer ,  Tarek Ibrahim ,  Adwait Telang ,  Dingying Xu ,  Leonel Arana ,  Xiaoying Guo ,  Ashay Dani ,  Sairam Agraharam ,  Haobo Chen ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Methods and apparatus to prevent over-etch in semiconductor packages are disclosed. A disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.

公开(公告)号：US12027466B2

公开(公告)日：2024-07-02

申请号：US17026703

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC: H01L23/538 ,  H01L21/768 ,  H05K1/11

CPC classification number: H01L23/5386 ,  H01L21/76838 ,  H01L23/5385 ,  H05K1/11

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US20220404551A1

公开(公告)日：2022-12-22

申请号：US17349305

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Zhichao Zhang ,  Brandon Marin ,  Tarek Ibrahim ,  Kemal Aygun ,  Stephen Smith

IPC: G02B6/12 ,  G02B6/122

Abstract: Integrated circuit packages may be formed having at least one optical via extending from a first surface of a package substrate to an opposing second surface of the package substrate. The at least one optical via creates an optical link between the opposing surfaces of the package substrate that enables the fabrication of a dual-sided optical multiple chip package, wherein integrated circuit devices can be attached to both surfaces of the package substrate for increased package density.

公开(公告)号：US20220102259A1

公开(公告)日：2022-03-31

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US20240331921A1

公开(公告)日：2024-10-03

申请号：US18739049

申请日：2024-06-10

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC: H01F27/28 ,  H01F41/32 ,  H01L23/498 ,  H01L23/64

CPC classification number: H01F27/2804 ,  H01F41/32 ,  H01L23/49827 ,  H01L23/645 ,  H01F2027/2809 ,  H01L23/49816

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.