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11.发明授权公开(公告)号：US09831167B1
公开(公告)日：2017-11-28
申请号：US15678130
申请日：2017-08-16
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yi-Fan Kao , Shuo-Hsun Chang , Yu-Te Lu , Kuo-Chun Huang
IPC: H01L23/498 , H01L23/31 , H01L23/13 , H01L23/00 , H01L21/56 , H01L23/538 , H01L21/48 , H01L23/367
CPC classification number: H01L23/49833 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/13 , H01L23/3114 , H01L23/3128 , H01L23/3142 , H01L23/367 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5389 , H01L23/562 , H01L24/16 , H01L24/81 , H01L25/105 , H01L2224/16227 , H01L2224/73204 , H01L2224/81191 , H01L2225/1023 , H01L2225/107 , H01L2924/12042 , H01L2924/15311 , H01L2924/1533 , H01L2924/15787 , H01L2924/18161 , H01L2924/3511 , H05K1/0206 , H05K1/0271 , H05K1/183 , H05K3/4697 , H05K2201/10378 , H05K2201/10734 , H05K2203/061 , H01L2924/00
Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with an opening bonded to a carrier board in order to form a compound carrier board structure. A die is placed in the opening and bonded to the carrier board. A sealant is filled in a gap between surrounding walls of the opening and the die at a height lower than the die to fixedly place the die within the opening and to leave a non-active surface of the die exposed.
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12.发明授权公开(公告)号：US09754870B2
公开(公告)日：2017-09-05
申请号：US15071368
申请日：2016-03-16
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yi-Fan Kao , Shuo-Hsun Chang , Yu-Te Lu , Kuo-Chun Huang
CPC classification number: H01L23/49833 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/13 , H01L23/3114 , H01L23/3128 , H01L23/3142 , H01L23/367 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5389 , H01L23/562 , H01L24/16 , H01L24/81 , H01L25/105 , H01L2224/16227 , H01L2224/73204 , H01L2224/81191 , H01L2225/1023 , H01L2225/107 , H01L2924/12042 , H01L2924/15311 , H01L2924/1533 , H01L2924/15787 , H01L2924/18161 , H01L2924/3511 , H05K1/0206 , H05K1/0271 , H05K1/183 , H05K3/4697 , H05K2201/10378 , H05K2201/10734 , H05K2203/061 , H01L2924/00
Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with a penetrating rectangular opening bonded to a non-conductive film then a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.
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公开(公告)号：US20150282306A1
公开(公告)日：2015-10-01
申请号：US14225671
申请日：2014-03-26
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu
CPC classification number: H05K3/4679 , H05K1/116 , H05K2201/0376
Abstract: A multilayer substrate structure includes a first plastic sheet, a second plastic sheet, a first circuit pattern layer, a second circuit pattern layer, and an interlayer connection pad. A first connection plug connected to the interlayer connection pad fills in a first opening of a first plastic sheet and is connected to a first connection pad of the first circuit pattern layer. A second connection plug fills a second opening of the second plastic sheet and is connected to a second connection pad of the second circuit pattern layer such that the second circuit pattern layer is electrically connected to the first circuit pattern layer via the interlayer connection pad. Therefore, even if there is little offset, it is possible to overcome the alignment tolerance and assure electrical connection between the circuit layers as desired.
Abstract translation: 多层基板结构包括第一塑料片，第二塑料片，第一电路图案层，第二电路图案层和层间连接垫。 连接到层间连接焊盘的第一连接插头填充第一塑料片的第一开口并连接到第一电路图案层的第一连接焊盘。 第二连接插头填充第二塑料片的第二开口并且连接到第二电路图案层的第二连接焊盘，使得第二电路图案层经由层间连接焊盘电连接到第一电路图案层。 因此，即使几乎没有偏移，也可以克服对准公差，并且根据需要确保电路层之间的电连接。
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公开(公告)号：US08941224B2
公开(公告)日：2015-01-27
申请号：US13853281
申请日：2013-03-29
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H01L23/06 , H01L23/498
CPC classification number: H01L23/49827 , H01L21/563 , H01L23/49861 , H01L23/49894 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/0002 , H01L2924/00
Abstract: A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.
Abstract translation: 封装结构包括薄片基板，稳定材料层，芯片和填充材料。 衬底的第一电路金属层嵌入电介质层中，并且由第一电路金属层和电介质层限定共面，并从电介质层露出。 衬底的接合焊盘在共面上，具有高于共面的高度并连接到第一电路金属层。 稳定材料层设置在共面的两侧，以限定用于容纳芯片的容纳空间。 将填充材料注入到接收空间中，用粘合垫牢固地固定芯片的销。 由于不需要塑料成型，所以包装结构的总厚度和成本降低。 稳定材料层防止基材翘曲和变形。
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公开(公告)号：US20140291853A1
公开(公告)日：2014-10-02
申请号：US13853281
申请日：2013-03-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H01L23/498
CPC classification number: H01L23/49827 , H01L21/563 , H01L23/49861 , H01L23/49894 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/0002 , H01L2924/00
Abstract: A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.
Abstract translation: 封装结构包括薄片基板，稳定材料层，芯片和填充材料。 衬底的第一电路金属层嵌入电介质层中，并且由第一电路金属层和电介质层限定共面，并从电介质层露出。 衬底的接合焊盘在共面上，具有高于共面的高度并连接到第一电路金属层。 稳定材料层设置在共面的两侧，以限定用于容纳芯片的容纳空间。 将填充材料注入到接收空间中，用粘合垫牢固地固定芯片的销。 由于不需要塑料成型，所以包装结构的总厚度和成本降低。 稳定材料层防止基材翘曲和变形。
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Patent Agency Ranking
16.发明授权公开(公告)号：US11044806B2
公开(公告)日：2021-06-22
申请号：US16718100
申请日：2019-12-17
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board.
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公开(公告)号：US10334719B2
公开(公告)日：2019-06-25
申请号：US15826692
申请日：2017-11-30
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally. Hence, costs for figuring out reasons of the unqualified electronic component can be reduced, and responsibilities for the unqualified electrical testing result of the electronic component can be clarified.
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18.发明申请公开(公告)号：US20190059154A1
公开(公告)日：2019-02-21
申请号：US15826694
申请日：2017-11-30
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a metallic delivery loading plate, a bottom-layer circuit structure, a conductive corrosion-barrier layer, and a multi-layer circuit structure. The bottom-layer circuit structure is overlapping on the delivery loading plate. The conductive corrosion-barrier layer is disposed on the bottom dielectric layer. The multi-layer circuit structure is overlapping on the bottom-layer circuit structure. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the inner-layer circuit of the multi-layer circuit structure and the bottom-layer circuit of the bottom-layer circuit structure. The delivery loading plate and the bottom dielectric layer of the bottom-layer circuit structure expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally.
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19.发明授权公开(公告)号：US09406641B2
公开(公告)日：2016-08-02
申请号：US13938335
申请日：2013-07-10
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yi-Fan Kao , Shuo-Hsun Chang , Yu-Te Lu , Kuo-Chun Huang
CPC classification number: H01L24/81 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/562 , H01L24/16 , H01L25/105 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81191 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15787 , H01L2924/18161 , H01L2924/3511 , H05K1/0206 , H05K1/0271 , H05K1/183 , H05K3/4697 , H05K2201/10378 , H05K2201/10734 , H05K2203/061 , H01L2924/00 , H01L2224/05599
Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate having a flip region with a through-opening and bonding to a Non-conductive Film to bond to a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.
Abstract translation: Flip-Chip Chip-Scale封装的复合载体板结构及其制造方法提供了一种具有通孔的翻转区和与非导电膜结合以结合到载体板以形成化合物载体的底板 板结构。 底板由低热膨胀系数材料构成。
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公开(公告)号：US09095084B2
公开(公告)日：2015-07-28
申请号：US13853303
申请日：2013-03-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
CPC classification number: H05K3/4647 , H05K1/0366 , H05K3/38
Abstract: A stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed.
Abstract translation: 一种堆叠多层结构，包括具有凸起的第一电路层，堆叠在第一电路层上以填充凸块之间的空间以形成共面的塑料膜，以及形成在共面上的第二电路层 并连接到第一电路层。 该塑料膜包括嵌入并不暴露的玻璃纤维层。
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