Abstract:
The present invention may include acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, determining a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals using a plurality of overlay algorithms, generating a plurality of overlay estimate distributions, and generating a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric a function of a width of a corresponding generated overlay estimate distribution, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target.
Abstract:
A method of determining OVL in a pattern in a semiconductor wafer manufacturing process comprises capturing images from a cell in a metrology target formed in at least two different layers in the wafer with parts of the target offset in opposing directions with respect to corresponding parts in a different layer. The images may be captured using radiation of multiple different wavelengths, each image including + 1 and - 1 diffraction patterns. A first and second differential signal may be determined for respective pixels in each image by subtracting opposing pixels from the + 1 and - 1 diffraction orders for each of the multiple wavelengths. An OVL for the respective pixels may be determined based on analyzing the differential signals from multiple wavelengths simultaneously. Then an OVL for the pattern may be determined as a weighted average of the OVL of the respective pixels. The weighting may be according to the sensitivity of the OVL to variation in wavelength.
Abstract:
Metrology methods and modules are provided, which comprise carrying out recipe setup procedure(s) and/or metrology measurement(s) using zonal analysis with respect to respective setup parameter(s) and/or metrology metric(s). The zonal analysis comprises relating to spatially variable values of the setup parameter(s) and/or metrology metric(s) across one or more wafers in one or more lots. Wafer zones may be discrete or spatially continuous, and be used to weight one or more parameter(s) and/or metric(s) during any of the stages of the respective setup and measurement processes.
Abstract:
Metrology methods are provided, which comprise identifying overlay critical patterns in a device design, the overlay critical patterns having an overlay sensitivity to process variation above a specified threshold that depends on design specifications; and using metrology targets that correspond to the identified overlay critical patterns. Alternatively or complementarily, metrology methods comprise identifying yield critical patterns according to a corresponding process window narrowing due to specified process variation, wherein the narrowing is defined by a dependency of edge placement errors (EPEs) of the patterns on process parameters. Corresponding targets and measurements are provided.
Abstract:
Imaging metrology targets and methods are provided, which combine 1D elements designed to provide one-dimensional (1D) imaging metrology signals along at least two measurement directions and 20 elements designed to provide at least one two-dimensional (2D) imaging metrology overlay signal. The target area of the 1D elements may enclose the 2D elements or the target areas of the 1D and 2D elements may be partially or fully congruent. The compound targets are small, possible multilayered, and may be designed to be process compatible (e.g., by segmentation of the elements, interspaces between elements and element backgrounds) and possibly be produced in die. 2D elements may be designed to periodic to provide additional one dimensional metrology signals.
Abstract:
Metrology methods and targets are provided, for estimating inter-cell process variation by deriving, from overlay measurements of at least three target cells having different designed misalignments, a dependency of a measured inaccuracy on the designed misalignments (each designed misalignment is between at least two overlapping periodic structures in the respective target cell). Inaccuracies which are related to the designed misalignments are reduced, process variation sources are detected and targets and measurement algorithms are optimized according to the derived dependency.
Abstract:
Targets, target elements and target design method are provided, which comprise designing a target structure to have a high contrast above a specific contrast threshold to its background in polarized light while having a low contrast below the specific contrast threshold to its background in non-polarized light. The targets may have details at device feature scale and be compatible with device design rules yet maintain optical contrast when measured with polarized illumination and thus be used effectively as metrology targets. Design variants and respective measurement optical systems are likewise provided.
Abstract:
Target designs methods and targets are provided, in which at least some of the differentiation between target elements and their background is carried out by segmenting either of them. Directed self-assembly (DSA) processes are used to generate fine segmentation, and various characteristics of the polymer lines and their guiding lines are used to differentiate target elements from their background. Target designs and design principles are disclosed in relation to the DSA process, as well as optimization of the DSA process to yield high metrology measurement accuracy in face of production inaccuracies. Furthermore, designs and methods are provided for enhancing and using ordered regions of a DSA-produced polymer surface as target elements and as hard masks for production processes. The targets and methods may be configured to enable metrology measurements using polarized light to distinguish target elements or DSA features.
Abstract:
In one embodiment, a semiconductor target for detecting overlay error between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The target comprises at least a plurality of a plurality of first grating structures having a course pitch that is resolvable by an inspection tool and a plurality of second grating structures positioned relative to the first grating structures. The second grating structures have a fine pitch that is smaller than the course pitch, and the first and second grating structures are both formed in two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate. The first and second gratings have feature dimensions that all comply with a predefined design rules specification.