Abstract:
A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.
Abstract:
A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.
Abstract:
An integrated circuit device has a digital device (600) operating at an internal core voltage (Vint); a linear voltage regulator (510); and an internal switched mode voltage regulator (180) controlled by the digital device and receiving an external supply voltage (Vext) being higher than the internal core voltage through at least first and second external pins (140a, 140b) and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component (182) through at least one further external pin (140c) of the plurality of external pins.
Abstract:
An integrated circuit device having at least one bond pad is coupled to a selectable plurality of input-output functionalities, e.g., an oscillator input, an analog input, an analog output, a digital input and a digital output. These analog, digital and oscillator functionalities may selectably share the same integrated circuit package external connection.
Abstract:
A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-todigital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.
Abstract:
Extending pulse width modulation phase offset when generating phase shifted groups of pulse width modulation (PWM) signals is accomplished with a separate phase counter that is independent of the time-base counters used in traditional PWM generation circuits and that is prevented from being re triggered until an existing duty cycle has completed. This is accomplished with a phase offset counter, a phase comparator and a circuit that is triggered via a master time base for overall synchronization of the multi-phase PWM signal generation.
Abstract:
A digital device generates a fixed duty cycle signal with an internal oscillator after a Power-On-Reset (POR), This fixed duty cycle signal is output on a signal pin that normally is used for a PWM control signal. The fixed duty cycle signal is used to stimulate the voltage generation circuits so as to power up the digital device for initialization thereof. Once the digital device has powered-up and initialized, the digital device switches over to normal operation for control of the power system.
Abstract:
Waveform errors between multiphase PWM signals caused by external synchronization signals is solved by providing a capture register in a master time base circuit. The capture register is triggered by the external sync signal so as to 'capture' the value of the master time base counter at the occurrence of the rising edge of the external sync signal. This captured counter value is then provided to the local time bases of each of the phase PMW signal generators as the effective PWM period instead of locally stored PWM period values of each PWM signal generator. The captured time base value provided to the individual PWM generator time bases insures that the individual PWM generators remain properly synchronized to the master time base throughout the PWM cycles of all of the phases.
Abstract:
Power supply modules have outputs coupled in parallel and convey load share balancing information over a single wire load share bus. Pulse width modulation (PWM) signals represent output loading of each of the power supply modules over the single wire load share bus. The PWM load share signal width (time asserted) of the PWM signal represents the output loading of the respective power supply module. Each of the power supply modules detect the assertion of the PWM signal on the load share bus and then each of them simultaneously drive the load share bus with a PWM signal representing their respective output loading. The power supply module having the greatest percent loading will assert its PWM load share signal longest, and the other power supply modules will thereafter adjust their outputs to more evenly supply power outputs to the load.