11.
    发明专利
    未知

    公开(公告)号:DE602005013978D1

    公开(公告)日:2009-05-28

    申请号:DE602005013978

    申请日:2005-08-12

    Inventor: KRIS BRYAN

    Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

    12.
    发明专利
    未知

    公开(公告)号:AT429073T

    公开(公告)日:2009-05-15

    申请号:AT05785003

    申请日:2005-08-12

    Inventor: KRIS BRYAN

    Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

    INTEGRATED CIRCUIT DEVICE WITH A LINEAR VOLTAGE REGULATOR AND AN INTERNAL SWITCHED MODE VOLTAGE REGULATOR
    13.
    发明申请
    INTEGRATED CIRCUIT DEVICE WITH A LINEAR VOLTAGE REGULATOR AND AN INTERNAL SWITCHED MODE VOLTAGE REGULATOR 审中-公开
    具有线性电压调节器和内部开关模式电压调节器的集成电路器件

    公开(公告)号:WO2013085992A3

    公开(公告)日:2014-02-06

    申请号:PCT/US2012067944

    申请日:2012-12-05

    CPC classification number: G06F1/26 G06F1/3203 H02M2001/0045

    Abstract: An integrated circuit device has a digital device (600) operating at an internal core voltage (Vint); a linear voltage regulator (510); and an internal switched mode voltage regulator (180) controlled by the digital device and receiving an external supply voltage (Vext) being higher than the internal core voltage through at least first and second external pins (140a, 140b) and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component (182) through at least one further external pin (140c) of the plurality of external pins.

    Abstract translation: 集成电路装置具有以内部核心电压(Vint)工作的数字装置(600); 线性稳压器(510); 和由数字装置控制的内部开关模式电压调节器(180),并通过至少第一和第二外部引脚(140a,140b)接收高于内部核心电压的外部电源电压(Vext),并产生内部核心电压 ,其中所述内部开关模式电压调节器通过所述多个外部引脚的至少一个另外的外部引脚(140c)与至少一个外部部件(182)耦合。

    AN INTEGRATED CIRCUIT DEVICE HAVING AT LEAST ONE BOND PAD WITH A SELECTABLE PLURALITY OF INPUT-OUTPUT FUNCTIONALITIES
    14.
    发明申请
    AN INTEGRATED CIRCUIT DEVICE HAVING AT LEAST ONE BOND PAD WITH A SELECTABLE PLURALITY OF INPUT-OUTPUT FUNCTIONALITIES 审中-公开
    一种集成电路器件,具有至少一键接垫,可选择多种输入 - 输出功能

    公开(公告)号:WO2008011408A2

    公开(公告)日:2008-01-24

    申请号:PCT/US2007073683

    申请日:2007-07-17

    CPC classification number: G06F13/4072 G06F13/4022

    Abstract: An integrated circuit device having at least one bond pad is coupled to a selectable plurality of input-output functionalities, e.g., an oscillator input, an analog input, an analog output, a digital input and a digital output. These analog, digital and oscillator functionalities may selectably share the same integrated circuit package external connection.

    Abstract translation: 具有至少一个键合焊盘的集成电路器件耦合到可选的多个输入 - 输出功能,例如振荡器输入,模拟输入,模拟输出,数字输入和数字输出。 这些模拟,数字和振荡器功能可以有选择地共享相同的集成电路封装外部连接。

    DIGITAL PROCESSOR WITH PULSE WIDTH MODULATION MODULE HAVING DYNAMICALLY ADJUSTABLE PHASE OFFSET CAPABILITY, HIGH SPEED OPERATION AND SIMULTANEOUS UPDATE OF MULTIPLE PULSE WIDTH MODULATION DUTY CYCLE REGISTERS
    15.
    发明申请
    DIGITAL PROCESSOR WITH PULSE WIDTH MODULATION MODULE HAVING DYNAMICALLY ADJUSTABLE PHASE OFFSET CAPABILITY, HIGH SPEED OPERATION AND SIMULTANEOUS UPDATE OF MULTIPLE PULSE WIDTH MODULATION DUTY CYCLE REGISTERS 审中-公开
    具有脉冲宽度调制模块的数字处理器具有动态可调相位偏移能力,高速操作和多脉冲宽度调制占空比寄存器的同时更新

    公开(公告)号:WO2006023427A2

    公开(公告)日:2006-03-02

    申请号:PCT/US2005028912

    申请日:2005-08-12

    Inventor: KRIS BRYAN

    CPC classification number: H03K7/08

    Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to­digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

    Abstract translation: 具有极高速度和高分辨率能力的脉宽调制(PWM)发生器,能够产生标准互补PWM,推挽PWM,可变偏移PWM,多相PWM,限流PWM,电流复位PWM和独立时基PWM 同时进一步提供相对于PWM信号精确定时的模数转换(ADC)模块的自动触发。 应用包括控制开关电源,其需要非常高的速度操作以在高开关频率下获得高分辨率,以及改变驱动电源功率部件的PWM输出信号之间的相位关系的能力。 与更新多个占空比寄存器相比,可以使用单个PWM占空比寄存器来一次更新任何和/或所有PWM发生器,以减少数字处理器的工作负载。

    SYSTEM, METHOD AND APPARATUS HAVING EXTENDED PULSE WIDTH MODULATION PHASE OFFSET
    16.
    发明申请
    SYSTEM, METHOD AND APPARATUS HAVING EXTENDED PULSE WIDTH MODULATION PHASE OFFSET 审中-公开
    具有扩展脉冲宽度调制相位偏移的系统,方法和装置

    公开(公告)号:WO2013048819A3

    公开(公告)日:2013-07-04

    申请号:PCT/US2012055895

    申请日:2012-09-18

    Inventor: KRIS BRYAN

    CPC classification number: H03K7/08

    Abstract: Extending pulse width modulation phase offset when generating phase shifted groups of pulse width modulation (PWM) signals is accomplished with a separate phase counter that is independent of the time-base counters used in traditional PWM generation circuits and that is prevented from being re triggered until an existing duty cycle has completed. This is accomplished with a phase offset counter, a phase comparator and a circuit that is triggered via a master time base for overall synchronization of the multi-phase PWM signal generation.

    Abstract translation: 当产生脉冲宽度调制(PWM)信号的相移组时,延长脉冲宽度调制相位偏移是通过独立于传统PWM生成电路中使用的时基计数器的单独的相位计数器实现的,并且被阻止被重新触发直到 现有的工作周期已经完成。 这是通过相位偏移计数器,相位比较器和经由主时基触发的用于多相PWM信号生成的总体同步的电路来实现的。

    DIGITAL DEVICE WITH BOOT STRAP CIRCUIT STIMULATOR
    17.
    发明申请
    DIGITAL DEVICE WITH BOOT STRAP CIRCUIT STIMULATOR 审中-公开
    带引导带电路刺激器的数字设备

    公开(公告)号:WO2011112821A3

    公开(公告)日:2012-05-03

    申请号:PCT/US2011027920

    申请日:2011-03-10

    CPC classification number: H02M1/36 H02M3/33515

    Abstract: A digital device generates a fixed duty cycle signal with an internal oscillator after a Power-On-Reset (POR), This fixed duty cycle signal is output on a signal pin that normally is used for a PWM control signal. The fixed duty cycle signal is used to stimulate the voltage generation circuits so as to power up the digital device for initialization thereof. Once the digital device has powered-up and initialized, the digital device switches over to normal operation for control of the power system.

    Abstract translation: 数字设备在上电复位(POR)之后,通过内部振荡器产生固定的占空比信号。该固定占空比信号在通常用于PWM控制信号的信号引脚上输出。 固定占空比信号用于激励电压产生电路,以便为数字设备供电以进行初始化。 一旦数字设备通电并初始化,数字设备将切换到正常操作,以控制电源系统。

    EXTERNALLY SYNCHRONIZING MULTIPHASE PULSE WIDTH MODULATION SIGNALS
    18.
    发明申请
    EXTERNALLY SYNCHRONIZING MULTIPHASE PULSE WIDTH MODULATION SIGNALS 审中-公开
    外部同步脉冲宽度调制信号的异步同步

    公开(公告)号:WO2009094352A3

    公开(公告)日:2009-10-08

    申请号:PCT/US2009031500

    申请日:2009-01-21

    Inventor: KRIS BRYAN

    CPC classification number: H03K7/08

    Abstract: Waveform errors between multiphase PWM signals caused by external synchronization signals is solved by providing a capture register in a master time base circuit. The capture register is triggered by the external sync signal so as to 'capture' the value of the master time base counter at the occurrence of the rising edge of the external sync signal. This captured counter value is then provided to the local time bases of each of the phase PMW signal generators as the effective PWM period instead of locally stored PWM period values of each PWM signal generator. The captured time base value provided to the individual PWM generator time bases insures that the individual PWM generators remain properly synchronized to the master time base throughout the PWM cycles of all of the phases.

    Abstract translation: 通过在主时基电路中提供捕获寄存器来解决由外部同步信号引起的多相PWM信号之间的波形误差。 捕获寄存器由外部同步信号触发,以便在外部同步信号的上升沿出现时捕获主时基计数器的值。 然后将该捕获的计数器值提供给每个相位PMW信号发生器的本地时基作为有效PWM周期,而不是每个PWM信号发生器的本地存储的PWM周期值。 提供给各个PWM发生器时基的捕获时基值确保各个PWM发生器在所有相的整个PWM周期内保持与主时基的正确同步。

    PULSE WIDTH MODULATION LOAD SHARE BUS
    20.
    发明申请
    PULSE WIDTH MODULATION LOAD SHARE BUS 审中-公开
    脉冲宽度调制负载分配总线

    公开(公告)号:WO2014124121A8

    公开(公告)日:2015-08-27

    申请号:PCT/US2014015079

    申请日:2014-02-06

    Inventor: KRIS BRYAN

    CPC classification number: H02M3/1584 G06F1/263 H02J1/102

    Abstract: Power supply modules have outputs coupled in parallel and convey load share balancing information over a single wire load share bus. Pulse width modulation (PWM) signals represent output loading of each of the power supply modules over the single wire load share bus. The PWM load share signal width (time asserted) of the PWM signal represents the output loading of the respective power supply module. Each of the power supply modules detect the assertion of the PWM signal on the load share bus and then each of them simultaneously drive the load share bus with a PWM signal representing their respective output loading. The power supply module having the greatest percent loading will assert its PWM load share signal longest, and the other power supply modules will thereafter adjust their outputs to more evenly supply power outputs to the load.

    Abstract translation: 电源模块具有并联耦合的输出,并通过单个有线负载共享总线传送负载共享平衡信息。 脉宽调制(PWM)信号表示单线负载共享总线上每个电源模块的输出负载。 PWM信号的PWM负载共享信号宽度(时间有效)表示相应电源模块的输出负载。 每个电源模块检测负载共享总线上的PWM信号的断言,然后它们每个都以表示其相应输出负载的PWM信号同时驱动负载共享总线。 具有最大负载百分比的电源模块将使其PWM负载共享信号最长,其他电源模块此后会调整其输出以更均匀地向负载提供电源输出。

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