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    Semiconductor device having improved frequency response
    12.
    发明专利
    Semiconductor device having improved frequency response 未知

    公开(公告)号：SG44601A1

    公开(公告)日：1997-12-19

    申请号：SG1996003547

    申请日：1992-09-14

    Applicant: MOTOROLA INC

    Inventor： BOLAND BERNARD W ,  DAVIES ROBERT B ,  SANDERS PAUL W

    IPC: H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L27/06

    Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

    14.
    发明专利
    未知

    公开(公告)号：DE69208297T2

    公开(公告)日：1996-09-05

    申请号：DE69208297

    申请日：1992-07-13

    Applicant: MOTOROLA INC

    Inventor： CAMBOU BERTRAND F ,  DAVIES ROBERT B

    IPC: H01L21/285 ,  H01L21/338 ,  H01L29/10 ,  H01L29/812

    Abstract: A semiconductor device having a channel region having a first and a second portion (13a, 13b). The first and second portions of the channel region (13a, 13b) are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.

    15.
    发明专利
    未知

    公开(公告)号：DE69232199T2

    公开(公告)日：2002-06-06

    申请号：DE69232199

    申请日：1992-09-14

    Applicant: MOTOROLA INC

    Inventor： BOLAND BERNARD W ,  DAVIES ROBERT B ,  SANDERS PAUL W

    IPC: H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06

    Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

    16.
    发明专利
    未知

    公开(公告)号：DE69619177D1

    公开(公告)日：2002-03-21

    申请号：DE69619177

    申请日：1996-08-22

    Applicant: MOTOROLA INC

    Inventor： DOW DIANN M ,  DAVIES ROBERT B ,  WILD ANDREAS A ,  ILDEREM VIDA

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/78

    Abstract: A method for forming a graded-channel field effect transistor includes providing a substrate (10) with an overlying gate electrode (14, 16). A spacer (23) is formed on only the drain side of the electrode. A graded-channel region (36) is formed aligned to the source side of the electrode while the spacer protects the drain side of the channel region. Source/drain regions (38) are formed, the spacer is removed, and then a drain extension region (40) is formed aligned to the drain side of the electrode.

    20.
    发明专利
    未知

    公开(公告)号：FR2522433A1

    公开(公告)日：1983-09-02

    申请号：FR8300702

    申请日：1983-01-18

    Applicant: MOTOROLA INC

    Inventor： DAVIES ROBERT B ,  DOTSON ROBERT N ,  MILLER IRA

    IPC: G11C11/14 ,  G11C7/06 ,  G11C19/08 ,  H03K5/02 ,  H03K5/24 ,  G01R19/145

    Abstract: A sense amplifier which is fully integrated has an on-chip voltage regulator to provide essentially error free operation. The sense amplifier provides peak-to-peak signal detection for comparison to a threshold voltage by a comparator. The output of the comparator is coupled to an RS flip-flop. The output of the RS flip-flop is coupled to a D flip-flop. The use of an RS flip-flop as well as a D flip-flop eliminates clocking problems caused by skewing and keeps a stored detected signal from changing prematurely.

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