公开(公告)号：BR0212235A

公开(公告)日：2004-12-28

申请号：BR0212235

申请日：2002-08-30

Applicant: QUALCOMM INC

Inventor： PELUSO VINCENZO FILIP ANDRE ,  BAZARJANI SEYFOLLAH ,  SHAH PETER JIVAN ,  JAFFEE JAMES

IPC: H04B1/16

Abstract: Techniques for processing incoming signals conforming to a plurality of standards or communication formats with a single baseband receive section are disclosed. In one aspect, a plurality of analog processing components are adjusted in response to a format select signal, set according to one of a plurality of supported formats or standards. In another aspect, the operating mode of an A/D converter is tuned in response to the format select signal. In yet another aspect, the response characteristics of a jammer filter are tuned in response to the format select signal. In yet another aspect, the adjustment of the plurality of analog processing components is carried out by varying the frequency of a sample clock in response to the format select signal. Various other aspects are also presented. These aspects have the benefit of allowing a single baseband receive section to be deployed to process analog signals conforming to a plurality of communications standards or formats, in a power and area efficient manner.

公开(公告)号：CA2482450A1

公开(公告)日：2003-10-23

申请号：CA2482450

申请日：2003-04-09

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH

IPC: H03H11/04 ,  H03H7/12 ,  H03H11/12

Abstract: A frequency response adjuster for a frequency responsive circuit, and a meth od for tuning a frequency response of a circuit, are disclosed. The adjuster ma y include a time constant sensor, wherein a charging state of the frequency responsive circuit may be measured by, and output from, the time constant sensor as a first voltage, a converter that samples the first voltage and outputs a second voltage resultant from a conversion of the first voltage by the converter, an array of trimming components, and a selector that utilizes the second voltage to select at least one trimming component from the array of trimming components. The method includes the steps of sensing a time constan t of the circuit, outputting the sensing as a first voltage, sampling the firs t voltage over a fixed interval, converting the sampled first voltage to a second voltage, and selecting, utilizing the second voltage, at least one trimming component from an array of trimming components. The time constant o f the circuit may be trimmed by the at least one trimming component selected.

公开(公告)号：AU2718702A

公开(公告)日：2002-05-15

申请号：AU2718702

申请日：2001-10-31

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH ,  WANG SEAN ,  PELUSO VINCENZO

IPC: H03M3/02

Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.

公开(公告)号：AT466410T

公开(公告)日：2010-05-15

申请号：AT02702127

申请日：2002-01-30

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH

IPC: H03M3/02 ,  H03H17/06

Abstract: A multi-stage circuit that includes a number of stages, with at least one stage being of a first type and at least one stage being of a second type. Each stage receives either a circuit input signal or an output signal from a preceding stage, processes (e.g., filters) the received signal, and provides a respective output signal. Each first type (or second type) stage operates based on one or more clock signals having a frequency of fS (or fS/N), where fS is the sampling frequency and N is an integer greater than one. Each first type stage may be implemented with a correlated double-sampling circuit, an auto-zeroing circuit, or a chopper stabilization circuit. Each second type stage may be implemented with a multi-sampling (i.e., double-sampling or higher order sampling) circuit. The multi-stage circuit may be designed to implement a lowpass filter, a DELTASIGMA ADC, or some other circuit.

公开(公告)号：CA2427423C

公开(公告)日：2009-09-29

申请号：CA2427423

申请日：2001-10-31

Applicant: QUALCOMM INC

Inventor： WANG SEAN ,  PELUSO VINCENZO ,  BAZARJANI SEYFOLLAH

IPC: H03M3/02

Abstract: A control mechanism that can be used to control a .SIGMA..DELTA. to provide the required level of performance while reducing power consumption. The .SIGMA..DELTA. ADC is designe dwith multiple stage (i.e., loops or sections) , and provides improved performance (e.g., higher dynamic range) as more stage s are enabled. The control mechanism selectively enables a sufficient number o f stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a .SIGMA..DELTA. ADC that is similar to the .SIGMA..DELTA. ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detecto r stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditined samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more .SIGMA..DELTA. stages in the .SIGMA..DELTA. ADC.

公开(公告)号：CA2576520A1

公开(公告)日：2006-02-23

申请号：CA2576520

申请日：2005-08-03

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH ,  OLIVEIRA LOUIS D

IPC: H04R19/00

公开(公告)号：AU2002238123A1

公开(公告)日：2002-09-19

申请号：AU2002238123

申请日：2002-02-22

Applicant: QUALCOMM INC

Inventor： ZHANG HAITAO ,  JHA SANJAY ,  BAZARJANI SEYFOLLAH ,  ZOU QUIZHEN

IPC: H01L25/18 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  G01R31/3167

Abstract: Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface.

公开(公告)号：CA2427423A1

公开(公告)日：2002-05-10

申请号：CA2427423

申请日：2001-10-31

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH ,  PELUSO VINCENZO ,  WANG SEAN

IPC: H03M3/02

Abstract: A control mechanism that can be used to control a .SIGMA..DELTA. to provide the required level of performance while reducing power consumption. The .SIGMA..DELTA. ADC is designe dwith multiple stage (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a .SIGMA..DELTA. ADC that is similar to the .SIGMA..DELTA. ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditined samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more .SIGMA..DELTA. stages in the .SIGMA..DELTA. ADC.

公开(公告)号：CA2437193C

公开(公告)日：2009-05-26

申请号：CA2437193

申请日：2002-01-30

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH ,  GOLDBLATT JEREMY

IPC: G05F3/26 ,  H03F3/45 ,  G05F3/08 ,  G05F3/20

Abstract: A bias circuit (126) is described for use in biasing an operational amplifie r (110) to maintain a constant transconductance divided by load capacitance (i.e. a constant gm/CL) despite temperature and process variations and despi te body effects. The bias circuit (126) includes a pair of current source devic es and a switched capacitor (SC) equivalent resistor circuit (136) for developi ng an equivalent resistance between the current source devices. By providing an SC equivalent resistor circuit clocked by non-overlapping fixed clock signal s, the gm/CL of the bias circuit is maintained substantially constant. Hence, a fixed bandwidth is maintained within the operation amplifier being biased. When employed in connection with operational amplifiers of an SC circuit, th e constant bandwidth enables the SC circuit to operate at a constant switching speed despite temp and process variation. Furthermore, by positioning the resistance equivalent circuit (136) between the current source devices of th e bias circuit, voltage differentials between the sources are eliminated there by removing any threshold voltage mismatch and thus compensating for body effec t variations.

公开(公告)号：DE60131027T2

公开(公告)日：2008-07-17

申请号：DE60131027

申请日：2001-10-31

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH ,  WANG SEAN ,  PELUSO VINCENZO

IPC: H03M3/02

Abstract: A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.