公开(公告)号：JP2012141993A

公开(公告)日：2012-07-26

申请号：JP2012024016

申请日：2012-02-07

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUS-SEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G06F21/24 ,  G06F12/00 ,  G06F21/00 ,  G06F21/20 ,  G06F21/22 ,  G11C7/24 ,  G11C16/02 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C16/22 ,  G11C2216/22

Abstract: PROBLEM TO BE SOLVED: To improve access time of flash memory and SRAM and reduce power consumption of an ASIC-based mobile telephone.SOLUTION: The flash memory and SRAM are embedded within an application specific integrated circuit (ASIC) to provide improved access times. The flash memory system includes a flash memory array 130 configured to provide a set of individual flash macros and a flash memory controller 132 for accessing the flash macros. The flash memory controller includes a write-while-reading unit 144, 146 for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers 138, and a password register 140 providing separate passwords for different portions of the flash memory array.

Abstract translation: 要解决的问题：改善闪存和SRAM的访问时间，并降低基于ASIC的移动电话的功耗。 解决方案：闪存和SRAM嵌入到专用集成电路（ASIC）中，以提供更好的访问时间。 闪存系统包括被配置为提供一组单独的闪存宏的闪存阵列130和用于访问闪存宏的闪存控制器132。 闪速存储器控制器包括写入同时读取单元144,146，用于在同时从另一个闪存宏读取时写入闪存宏中的一个。 闪速存储器控制器还包括可编程等待状态寄存器138和密码寄存器140，为闪存阵列的不同部分提供单独的密码。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2011192290A

公开(公告)日：2011-09-29

申请号：JP2011092137

申请日：2011-04-18

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUS-SEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/16 ,  G06F21/00 ,  G06F21/24 ,  G11C7/24 ,  G11C16/02 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C16/22 ,  G11C2216/22

Abstract: PROBLEM TO BE SOLVED: To minimize the time required for each access from a flash memory. SOLUTION: A mobile communication device includes a wait state memory register 138 for flash bus wait states that is used in using different portions of a flash memory array. The wait state specifies such the number of cycles of a flash memory bus that a flash memory access unit has to wait until a retrieval of data by a read-out operation. Different wait state values are provided in different portions of the flash memory array so as to adjust different degradation levels of the flash memory array. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：最大限度地减少每次从闪存访问所需的时间。 解决方案：移动通信设备包括用于使用闪存阵列的不同部分的闪存总线等待状态的等待状态存储器寄存器138。 等待状态指定闪速存储器访问单元必须等待直到通过读出操作检索数据的闪存总线的周期数。 在闪速存储器阵列的不同部分提供不同的等待状态值，以便调整闪存阵列的不同劣化水平。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009152616A

公开(公告)日：2009-07-09

申请号：JP2009000324

申请日：2009-01-05

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： BAZARJANI SEYFOLLAH ,  ZHANG HAITAO ,  ZOU QUIZHEN ,  JHA SANJAY

IPC: H01L21/822 ,  H01L25/18 ,  H01L23/31 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L27/04

CPC classification number: H01L25/0657 ,  G01R31/2853 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06164 ,  H01L2224/06165 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1435 ,  H01L2924/145 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To provide a technique that assembles an analog circuit and a digital circuit on separate dies and laminates the dies in a single package to form a mixed-signal IC that provides many benefits. SOLUTION: The analog circuit and digital circuit are mounted on two separate dies using a different IC process suitable for different types of circuits. Thereafter, the analog die 130 and digital die 120 are integrated (laminated), and are encapsulated in the single package 110. Bonding pads 112, 122, 124, 132, 134 are provided to interconnect the dies and connect the dies to external pins. The bonding pads 112, 122, 124, 132, 134 can be positioned and arranged in a method supplying a required connectivity while minimizing the die region quantities required for mounting the pads. The connectivity between the dies can be tested together with a serial bus interface. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在单独的管芯上组装模拟电路和数字电路的技术，并且将单个封装中的管芯叠层以形成提供许多益处的混合信号IC。 解决方案：模拟电路和数字电路使用适合不同类型电路的不同IC工艺安装在两个独立的裸片上。 此后，将模拟管芯130和数字管芯120集成（层叠），并被封装在单个封装件110中。提供接合焊盘112,122,124,132,134以互连模具并将管芯连接到外部引脚。 接合焊盘112,122,124,132,134可以以提供所需连接性的方式定位和布置，同时最小化安装焊盘所需的管芯区域数量。 模块之间的连接可以与串行总线接口一起测试。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2012141994A

公开(公告)日：2012-07-26

申请号：JP2012024017

申请日：2012-02-07

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUS-SEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/02 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C16/22 ,  G11C2216/22

Abstract: PROBLEM TO BE SOLVED: To provide a flash memory system where a boot loader is swapped into high memory such that other data and programs can be stored within low memory where they can be accessed more expediently.SOLUTION: The flash memory system includes flash memory cells and a flash memory controller 132 provided with means for partitioning the flash memory cells into high and low memory locations. The flash memory cells store a boot loader beginning at a lowest memory address of the flash memory space. The means for partitioning includes means for swapping the high and low memory locations after operations performed by the boot loader have been completed. A memory swap unit 149 is provided for swapping the high and low memory subsequent to the completion of operations performed by the boot loader.

Abstract translation: 要解决的问题：提供一种闪存系统，其中引导加载器被交换到高存储器中，使得其他数据和程序可以被存储在低内存中，从而可以更方便地访问它们。 闪存系统包括闪存单元和闪速存储器控制器132，闪存控制器132具有用于将闪存单元分成高和低存储器位置的装置。 闪存单元存储从闪存空间的最低存储器地址开始的引导加载程序。 用于分区的装置包括用于在由引导加载器执行的操作已经完成之后交换高和低存储器位置的装置。 提供存储器交换单元149，用于在由引导加载程序执行的操作完成之后交换高和低存储器。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：AU2271301A

公开(公告)日：2001-06-25

申请号：AU2271301

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：AU2108701A

公开(公告)日：2001-06-25

申请号：AU2108701

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： SIMMONDS STEPHEN MARK ,  JHA SANJAY

IPC: G11C7/10 ,  G11C16/10 ,  G11C16/26

公开(公告)号：CA2393143A1

公开(公告)日：2001-06-21

申请号：CA2393143

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  YU NICHOLAS K ,  KHAN SAFI ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL

IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C16/32

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：US6392925B2

公开(公告)日：2002-05-21

申请号：US81818601

申请日：2001-03-26

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C7/00

CPC classification number: G11C16/26 ,  G11C16/22 ,  G11C2216/22

Abstract: The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory. Thus, portions of flash memory subject to flash memory degradation may be programmed with a higher number of wait states than portions of memory that are not subject to degradation.

Abstract translation: 闪存和SRAM存储器嵌入到专用集成电路（ASIC）中，以提供改进的访问时间，并且还降低采用ASIC的移动电话的总体功耗。 闪存系统包括被配置为提供一组单独的闪存宏的闪存阵列和用于访问闪存宏的闪存控制器。 闪速存储器控制器包括一个写入单元，用于写入其中一个闪存宏，同时从另一个闪存宏读取。 通过在写入时允许读取，读取操作不需要延迟，直到完成等待写入操作。 闪存控制器还包括可编程等待状态寄存器。 每个等待状态寄存器存储与闪存的一部分相关联的可编程数量的闪存总线等待状态。 因此，存在闪速存储器劣化的闪存的部分可以被编程为具有比没有劣化的存储器部分更多的等待状态。

公开(公告)号：DE10162002T1

公开(公告)日：2010-12-09

申请号：DE10162002

申请日：2006-09-26

Applicant: QUALCOMM INC

Inventor： ROMINE CHRISTOPHER ,  FEENAGHTY DENNIS ,  BURKE JOSEPH ,  JHA SANJAY ,  SOLIMAN SAMIR

IPC: G06Q10/00 ,  H04W24/00 ,  H04W24/06 ,  H04W88/02

公开(公告)号：DE60030765T2

公开(公告)日：2007-09-13

申请号：DE60030765

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU K ,  KHAN SAFI

IPC: G06F12/06 ,  G11C7/24 ,  G06F12/00 ,  G06F21/00 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.