公开(公告)号：AR060366A1

公开(公告)日：2008-06-11

申请号：ARP070101458

申请日：2007-04-04

Applicant: QUALCOMM INC

Inventor： SUBRAHMANYAM JAI N ,  GANAPATHY CHINNAPPA K ,  VAN VEEN DURK L ,  COUSINEAU KEVIN STUART ,  OH SEOL-YONG

IPC: G06F17/14 ,  H04L27/26

Abstract: Se describen técnicas para ejecutar entubado de IFFT. En algunos aspectos, el entubamiento se logra con un sistema de procesamiento con una memoria con secciones primera, segunda y tercera, un codificador configurado para procesar datos en cada una de las secciones de memoria primera, segunda y tercera en forma de círculo, un IFFT configurado para procesar los datos codificados en cada una de las secciones primera segunda y tercera en forma de círculo, y un post-procesador configurado para procesar los datos procesados por IFFT en cada una de las secciones de memoria primera, segunda y tercera en forma de círculo.

公开(公告)号：DE602004017351D1

公开(公告)日：2008-12-04

申请号：DE602004017351

申请日：2004-12-03

Applicant: QUALCOMM INC

Inventor： KRISHNAMOORTHI RAGHURAMAN ,  GANAPATHY CHINNAPPA K

IPC: G06F17/14 ,  G06F15/00 ,  H04L27/26

Abstract: A Fast Fourier Transform (FFT) hardware implementation and method provides efficient FFT processing while minimizing the die area needed in an Integrated Circuit (IC). The FFT hardware can implement an N point FFT, where N=rn is a function of a radix (r). The hardware implementation includes a sample memory having N/r rows, each storing r samples. A twiddle factor memory can store k twiddle factors per row, where 0

公开(公告)号：AT412220T

公开(公告)日：2008-11-15

申请号：AT04812920

申请日：2004-12-03

Applicant: QUALCOMM INC

Inventor： KRISHNAMOORTHI RAGHURAMAN ,  GANAPATHY CHINNAPPA K

IPC: G06F17/14 ,  G06F15/00 ,  H04L27/26

Abstract: A Fast Fourier Transform (FFT) hardware implementation and method provides efficient FFT processing while minimizing the die area needed in an Integrated Circuit (IC). The FFT hardware can implement an N point FFT, where N=rn is a function of a radix (r). The hardware implementation includes a sample memory having N/r rows, each storing r samples. A twiddle factor memory can store k twiddle factors per row, where 0

公开(公告)号：AR060370A1

公开(公告)日：2008-06-11

申请号：ARP070101462

申请日：2007-04-04

Applicant: QUALCOMM INC

Inventor： BAI JINXIA ,  GANAPATHY CHINNAPPA K ,  SUN THOMAS

IPC: H04L12/56

Abstract: Métodos y aparato para el mapeo dinámico del paquete. Se provee un método para mapear datos métricos para producir un paquete decodificable asociado con un canal. El método incluye la obtencion de un identificador del canal asociado con datos métricos, la determinacion de un buffer disponible de una pluralidad de buffers basado en el identificador del canal, escribir los datos métricos en el buffer disponible, la deteccion de cuando un paquete decodificable está formado en un buffer seleccionado de la pluralidad de buffers, y sacar el paquete decodificable desde el buffer seleccionado. Un aparato incluye una pluralidad de buffers y logica de mapeo que está configurado para obtener un identificador del canal asociado con los datos métricos, determinar un buffer disponible basado en el identificador del canal, escribir los datos métricos en el buffer disponible, detectar cuando un paquete decodificable está formado en un buffer seleccionado, y sacar el paquete decodificable desde el buffer seleccionado.

公开(公告)号：NO20075179A

公开(公告)日：2007-12-10

申请号：NO20075179

申请日：2007-10-10

Applicant: QUALCOMM INC

Inventor： WANG MICHAEL MAO ,  JAROSINSKI TADEUSZ ,  GANAPATHY CHINNAPPA K

IPC: H04B1/16

CPC classification number: H04W52/0225 ,  H04B1/1615 ,  H04W52/0293 ,  Y02D70/1222 ,  Y02D70/1242 ,  Y02D70/164 ,  Y02D70/40

Abstract: Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

公开(公告)号：BRPI0618501A2

公开(公告)日：2011-09-06

申请号：BRPI0618501

申请日：2006-11-09

Applicant: QUALCOMM INC

Inventor： WANG MICHAEL MAO ,  GANAPATHY CHINNAPPA K ,  BAI JINXIA

IPC: H04B1/16

Abstract: Apparatus and methods for estimating the frequency of a sleep or slow clock using a fast clock, such as a temperature compensated crystal oscillator. The disclosed apparatus include an estimator having a first counter that receives sleep clock synchronized pulses issuing each cycle of the sleep clock period, yet are synchronized to a fast clock. The slow clock synchronized pulses are counted up to a predetermined number; whereupon a full count signal is issued. A second counter receives the full count signal and increments each time the full count signal is received. A third counter counts fast clock cycles until the full count signal occurs. Based on the number of counts of the slow and fast clock cycles, the frequency of the slow clock may be determined using only the domain of the fast clock for performing the measurement thereby tying accuracy of the measurement to the accuracy of the fast clock. The disclosed apparatus also include an integrated circuit and a transceiver employing the disclosed estimator. Corresponding methods are also disclosed.

公开(公告)号：BRPI0608226A2

公开(公告)日：2009-11-24

申请号：BRPI0608226

申请日：2006-03-13

Applicant: QUALCOMM INC

Inventor： JAROSINSKI TADEUSZ ,  WANG MICHAEL MAO ,  GANAPATHY CHINNAPPA K

IPC: H04B1/16 ,  H04M1/73

Abstract: Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

公开(公告)号：CA2629456A1

公开(公告)日：2007-05-18

申请号：CA2629456

申请日：2006-11-09

Applicant: QUALCOMM INC

Inventor： WANG MICHAEL MAO ,  GANAPATHY CHINNAPPA K ,  BAI JINXIA

IPC: H04B1/16

Abstract: Apparatus and methods for estimating the frequency of a sleep or slow clock using a fast clock, such as a temperature compensated crystal oscillator. The disclosed apparatus include an estimator having a first counter that receives sleep clock synchronized pulses issuing each cycle of the sleep clock period, yet are synchronized to a fast clock. The slow clock synchronized pulses are counted up to a predetermined number; whereupon a full count signal is issued. A second counter receives the full count signal and increments each time the full count signal is received. A third counter counts fast clock cycles until the full count signal occurs. Based on the number of counts of the slow and fast clock cycles, the frequency of the slow clock may be determined using only the domain of the fast clock for performing the measurement thereby tying accuracy of the measurement to the accuracy of the fast clock. The disclosed apparatus also include an integrated circuit and a transceiver employing the disclosed estimator. Corresponding methods are also disclosed.

公开(公告)号：BRPI0417222A

公开(公告)日：2007-02-21

申请号：BRPI0417222

申请日：2004-12-03

Applicant: QUALCOMM INC

Inventor： KRISHNAMOORTHI RAGHURAMAN ,  GANAPATHY CHINNAPPA K

IPC: G06F15/00 ,  G06F17/14 ,  H04L27/26

Abstract: A Fast Fourier Transform (FFT) hardware implementation and method provides efficient FFT processing while minimizing the die area needed in an Integrated Circuit (IC). The FFT hardware can implement an N point FFT, where N=rn is a function of a radix (r). The hardware implementation includes a sample memory having N/r rows, each storing r samples. A twiddle factor memory can store k twiddle factors per row, where 0

公开(公告)号：MXPA06006391A

公开(公告)日：2006-08-23

申请号：MXPA06006391

申请日：2004-12-03

Applicant: QUALCOMM INC

Inventor： GANAPATHY CHINNAPPA K

IPC: G06F15/00 ,  H04L27/26 ,  G06F17/14

Abstract: Una implementacion y un metodo de hardware de transformacion de Fourier Rapida (FFT) proporciona procesamiento de FFT eficiente mientras que reduce al minimo el area de chip necesaria en un Circuito Integrado (CI). El hardware de FFT puede implementar una FFT de punto N, en donde N = rn es una funcion de una raiz (r). La implementacion de hardware incluye una memoria de muestras que tiene N/r filas, cada una que almacena r muestras. Una memoria de factor de giro puede almacenar k factores de giro por fila, en donde 0