公开(公告)号：DE602005016794D1

公开(公告)日：2009-11-05

申请号：DE602005016794

申请日：2005-05-18

Applicant: QUALCOMM INC

Inventor： SUBRAHMANYAM JAI N ,  COUSINEAU KEVIN S ,  WANG MICHAEL

IPC: H04L27/26

Abstract: In an OFDM system, multiple (M) interlaces are defined for M non-overlapping sets of frequency subbands, and M slots with fixed indices are also defined. Data streams and pilot are mapped to slots, which are in turn mapped to interlaces based on a slot-to-interlace mapping scheme that can achieve frequency diversity and good performance for all slots. At a transmitter, a slot-to-interlace converter maps the slots to the interlaces. The slot-to-interlace converter includes multiple multiplexers and a control unit. The multiplexers map the M slots to the M interlaces based on the slot-to-interlace mapping scheme. The control unit generates at least one control signal for the multiplexers. The multiplexers may be arranged and controlled in various manners depending on the slot-to-interlace mapping scheme. At a receiver, a complementary interlace-to-slot converter maps the interlaces to the slots.

公开(公告)号：AR049428A1

公开(公告)日：2006-08-02

申请号：ARP050102050

申请日：2005-05-18

Applicant: QUALCOMM INC

Inventor： SUBRAHMANYAM JAI N ,  COUSINEAU KEVIN S ,  WANG MICHAEL

IPC: H04L27/26

Abstract: En un sistema OFDM, los entrelaces multiples (M) se definen para conjuntos de sub-bandas de frecuencia que no se superponen M, y también se definen las ranuras M con índices fijos. Los flujos de datos y las ondas piloto se distribuyen en ranuras que, a su vez, son distribuidas en entrelaces en base a un esquema de distribucion ranura-a-entrelace que puede lograr diversidad de frecuencia y un buen rendimiento para todas las ranuras. En un transmisor, un conversor ranura-a-entrelace distribuye las ranuras en los entrelaces. El conversor ranura-a-entrelace incluye varios multiplexores y una unidad de control. Los multiplexores distribuyen las ranuras M en los entrelaces M en base a un esquema de distribucion ranura-a-entrelace. La unidad de control genera, por lo menos una senal de control para los multiplexores. Los multiplexores pueden ordenarse y controlarse de distintas maneras segun el esquema de distribucion ranura-a-entrelace. En un receptor, un conversor entrelace- a-ranura complementario distribuye los entrelaces en las ranuras.

公开(公告)号：AR060372A1

公开(公告)日：2008-06-11

申请号：ARP070101464

申请日：2007-04-04

Applicant: QUALCOMM INC

Inventor： CHARI MURALI RAMASWAMY ,  BAI JINXIA ,  VAN VEEN DURK L ,  SUBRAHMANYAM JAI N

IPC: H04B7/005

Abstract: Un sistema de distribucion multimedia. El sistema de distribucion incluye una unidad transmisora que distribuye contenido desde un proveedor de contenido a una o más unidades suscriptoras inalámbricas. La unidad transmisora incluye un decodificador configurado para determinar si una pluralidad de paquetes entrantes incluyen uno o mas paquetes borrados, un transmisor configurado para transmitir los paquetes a una unidad receptora, y un generador de codigo de deteccion de error configurado para generar un codigo de deteccion de error para cada uno de los paquetes transmitidos a la unidad receptora, estando el codigo de deteccion de error modificado para cada uno de los paquetes borrados de manera tal que la unidad receptora podrá identificar los paquetes borrados.

公开(公告)号：CA2566727A1

公开(公告)日：2005-12-01

申请号：CA2566727

申请日：2005-05-18

Applicant: QUALCOMM INC

Inventor： WANG MICHAEL ,  COUSINEAU KEVIN S ,  SUBRAHMANYAM JAI N

IPC: H04L27/26

Abstract: In an OFDM system, multiple (M) interlaces are defined for M non-overlapping sets of frequency subbands, and M slots with fixed indices are also defined. Data streams and pilot are mapped to slots, which are in turn mapped to interlaces based on a slot-to-interlace mapping scheme that can achieve frequency diversity and good performance for all slots. At a transmitter, a slot-to-interlace converter maps the slots to the interlaces. The slot-to-interlace converter includes multiple multiplexers and a control unit. The multiplexers map the M slots to the M interlaces based on the slot-to-interlace mapping scheme. The control unit generates at least one control signal for the multiplexers. The multiplexers may be arranged and controlled in various manners depending on the slot-to-interlace mapping scheme. At a receiver, a complementary interlace-to-slot converter maps the interlaces to the slots.

公开(公告)号：BRPI0712835A2

公开(公告)日：2012-07-24

申请号：BRPI0712835

申请日：2007-04-24

Applicant: QUALCOMM INC

Inventor： BALRAJ SAJITH ,  COLLINS BRUCE ,  SAIDI BEN ,  SUBRAHMANYAM JAI N ,  RILEY ROBERT ,  YOUNKIN KENTON A

IPC: H04W4/18

Abstract: Multiplexer to transmitter interface protocol. A method for a data interface protocol is provided that includes receiving a first packet stream having at least one overhead information symbol (OIS) group and at least one multicast logical channel (MLC) group, and mapping each OIS group to an OIS descriptor packet and at least one OIS payload packet. The method also includes mapping each MLC group to an MLC descriptor packet and at least one MLC payload packet, and outputting the OIS descriptor, OIS payload, MLC descriptor, and MLC payload packets in a second packet stream. An apparatus includes input logic to receive the first packet stream, processing logic to map each OIS group to an OIS descriptor packet an OIS payload packet, and each MLC group to an MLC descriptor packet and an MLC payload packet, and output logic to output the mapped packets in a second packet stream.

公开(公告)号：AR060366A1

公开(公告)日：2008-06-11

申请号：ARP070101458

申请日：2007-04-04

Applicant: QUALCOMM INC

Inventor： SUBRAHMANYAM JAI N ,  GANAPATHY CHINNAPPA K ,  VAN VEEN DURK L ,  COUSINEAU KEVIN STUART ,  OH SEOL-YONG

IPC: G06F17/14 ,  H04L27/26

Abstract: Se describen técnicas para ejecutar entubado de IFFT. En algunos aspectos, el entubamiento se logra con un sistema de procesamiento con una memoria con secciones primera, segunda y tercera, un codificador configurado para procesar datos en cada una de las secciones de memoria primera, segunda y tercera en forma de círculo, un IFFT configurado para procesar los datos codificados en cada una de las secciones primera segunda y tercera en forma de círculo, y un post-procesador configurado para procesar los datos procesados por IFFT en cada una de las secciones de memoria primera, segunda y tercera en forma de círculo.

公开(公告)号：CA2648107A1

公开(公告)日：2007-11-08

申请号：CA2648107

申请日：2007-04-24

Applicant: QUALCOMM INC

Inventor： SAIDI BEN ,  COLLINS BRUCE ,  RILEY ROBERT ,  SUBRAHMANYAM JAI N ,  BALRAJ SAJITH ,  YOUNKIN KENTON A

IPC: H04W80/00 ,  H04W4/18 ,  H04W80/06

Abstract: Multiplexer to transmitter interface protocol. A method for a data interf ace protocol is provided that includes receiving a first packet stream havin g at least one overhead information symbol (OIS) group and at least one mult icast logical channel (MLC) group, and mapping each OIS group to an OIS desc riptor packet and at least one OIS payload packet. The method also includes mapping each MLC group to an MLC descriptor packet and at least one MLC payl oad packet, and outputting the OIS descriptor, OIS payload, MLC descriptor, and MLC payload packets in a second packet stream. An apparatus includes inp ut logic to receive the first packet stream, processing logic to map each OI S group to an OIS descriptor packet an OIS payload packet, and each MLC grou p to an MLC descriptor packet and an MLC payload packet, and output logic to output the mapped packets in a second packet stream.

公开(公告)号：WO2007115330A3

公开(公告)日：2007-12-13

申请号：PCT/US2007066003

申请日：2007-04-04

Applicant: QUALCOMM INC ,  SUBRAHMANYAM JAI N ,  GANAPATHY CHINNAPPA K ,  VAN VEEN DURK L ,  BAI JINXIA ,  COUSINEAU KEVIN STUART ,  OH SEOKYONG

Inventor： SUBRAHMANYAM JAI N ,  GANAPATHY CHINNAPPA K ,  VAN VEEN DURK L ,  BAI JINXIA ,  COUSINEAU KEVIN STUART ,  OH SEOKYONG

IPC: H04L27/26

CPC classification number: H04L27/2626

Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.

Abstract translation: 描述了用于执行IFFT流水线的技术。 在一些方面，流水线通过具有具有第一，第二和第三部分的存储器的处理系统来实现，编码器被配置为以循环方式处理第一，第二和第三存储器部分中的每一个中的数据，IFFT被配置 以循环方式处理第一，第二和第三部分中的每一个中的编码数据，以及后处理器，其被配置为以循环方式处理第一，第二和第三存储器部分中的每一个中的经IFFT处理的数据 。

公开(公告)号：WO2007127761A9

公开(公告)日：2008-02-28

申请号：PCT/US2007067347

申请日：2007-04-24

Applicant: QUALCOMM INC ,  BALRAJ SAJITH ,  COLLINS BRUCE ,  SAIDI BEN ,  SUBRAHMANYAM JAI N ,  RILEY ROBERT ,  YOUNKIN KENTON A

Inventor： BALRAJ SAJITH ,  COLLINS BRUCE ,  SAIDI BEN ,  SUBRAHMANYAM JAI N ,  RILEY ROBERT ,  YOUNKIN KENTON A

IPC: H04W4/18

CPC classification number: H04L12/189 ,  H04L29/06027 ,  H04L65/4076 ,  H04L65/605 ,  H04W4/18

Abstract: Multiplexer to transmitter interface protocol. A method for a data interface protocol is provided that includes receiving a first packet stream having at least one overhead information symbol (OIS) group and at least one multicast logical channel (MLC) group, and mapping each OIS group to an OIS descriptor packet and at least one OIS payload packet. The method also includes mapping each MLC group to an MLC descriptor packet and at least one MLC payload packet, and outputting the OIS descriptor, OIS payload, MLC descriptor, and MLC payload packets in a second packet stream. An apparatus includes input logic to receive the first packet stream, processing logic to map each OIS group to an OIS descriptor packet an OIS payload packet, and each MLC group to an MLC descriptor packet and an MLC payload packet, and output logic to output the mapped packets in a second packet stream.

Abstract translation: 多路复用器到发射机接口协议。 提供了一种用于数据接口协议的方法，包括接收具有至少一个开销信息符号（OIS）组和至少一个多播逻辑信道（MLC）组的第一分组流，并将每个OIS组映射到OIS描述符分组， 至少一个OIS有效载荷分组。 该方法还包括将每个MLC组映射到MLC描述符分组和至少一个MLC有效载荷分组，并且在第二分组流中输出OIS描述符，OIS有效载荷，MLC描述符和MLC有效载荷分组。 一种装置包括用于接收第一分组流的输入逻辑，处理逻辑以将每个OIS组映射到OIS描述符分组OIS有效载荷分组，以及将每个MLC组映射到MLC描述符分组和MLC有效载荷分组，以及输出逻辑以输出 在第二分组流中映射分组。

公开(公告)号：WO2007115328A3

公开(公告)日：2007-12-13

申请号：PCT/US2007066001

申请日：2007-04-04

Applicant: QUALCOMM INC ,  SUBRAHMANYAM JAI N ,  GANAPATHY CHINNAPPA K ,  VAN VEEN DURK L ,  BAI JINXIA ,  COUSINEAU KEVIN STUART ,  OH SEOKYONG

Inventor： SUBRAHMANYAM JAI N ,  GANAPATHY CHINNAPPA K ,  VAN VEEN DURK L ,  BAI JINXIA ,  COUSINEAU KEVIN STUART ,  OH SEOKYONG

IPC: H04L27/26

CPC classification number: H04L27/2626

Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

Abstract translation: 描述了用于执行IFFT流水线的技术。 在一些方面，流水线通过具有具有第一和第二部分的存储器的处理系统来实现，编码器被配置为处理第一和第二存储器部分中的每一个中的数据;被配置为处理第一和第二部分中的编码数据的IFFT 存储器部分和后处理器，其被配置为在IFFT处理第二存储器部分中的编码数据时处理第一存储器部分中的IFFT处理的数据，后处理器被配置为以与编码器不同的时钟速度操作 IFFT。