公开(公告)号：AT339764T

公开(公告)日：2006-10-15

申请号：AT00986483

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：CA2704893A1

公开(公告)日：2001-06-21

申请号：CA2704893

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G11C16/02 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：AT465552T

公开(公告)日：2010-05-15

申请号：AT06738523

申请日：2006-03-13

Applicant: QUALCOMM INC

Inventor： KHAN SAFI

IPC: H03M13/29

Abstract: A system and method are provided for parallel path turbo decoding in a portable wireless communications user terminal (UT). The method accepts a coded stream having a first order of information packets, and demultiplexes the coded stream into first coded and second coded information streams. The first coded stream is turbo decoded, generating a first decoded information stream. Likewise, the second coded stream is decoded to generate a second decoded information stream, asynchronously with respect to the first decoded stream. Then, the first and second decoded streams are combined into a combined stream having the first order of decoded information packets. The first and second decoded streams are combined by parallel buffering the first and second decoded streams, generating parallel-buffered decoded streams. Then, the parallel-buffered decoded streams are multiplexed to create a combined stream, which is stored in an output buffer.

公开(公告)号：DE60030765D1

公开(公告)日：2006-10-26

申请号：DE60030765

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU K ,  KHAN SAFI

IPC: G06F12/06 ,  G11C7/24 ,  G06F12/00 ,  G06F21/00 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：CA2704894A1

公开(公告)日：2001-06-21

申请号：CA2704894

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G11C16/02 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/06 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：HUE048956T2

公开(公告)日：2020-08-28

申请号：HUE15716287

申请日：2015-03-26

Applicant: QUALCOMM INC

Inventor： WYRWAS JOHN MICHAEL ,  KHAN SAFI ,  GOUSEV EVGENI PETROVICH ,  GRUHLKE RUSSELL WAYNE ,  ZHOU YING ,  WECKERLE FRANK FREDERICK

IPC: G06F21/32 ,  G06K9/00 ,  G06K9/20 ,  G06K9/22

公开(公告)号：AT477526T

公开(公告)日：2010-08-15

申请号：AT01908942

申请日：2001-02-07

Applicant: QUALCOMM INC

Inventor： KHAN SAFI ,  YU NICHOLAS ,  HASQUINE DAVID ,  FUCHS ROBERT ,  STAFFORD DAVE ,  DHAWAN RAJAT

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30 ,  G06F9/38

公开(公告)号：HK1064758A1

公开(公告)日：2005-02-04

申请号：HK04107337

申请日：2004-09-23

Applicant: QUALCOMM INC

Inventor： KHAN SAFI ,  YU NICHOLAS ,  PAN HANFANG

IPC: G06F20060101 ,  G06F13/26

Abstract: A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the microprocessor. The microprocessor has components for responding to interrupt requests by interrupting current processing and performing an interrupt service routine associated with the interrupt request. The interrupt controller receives interrupt requests directed to the microprocessor from the peripheral processing units and for prioritizes the interrupt requests on behalf of the microprocessor. By providing an interrupt controller for prioritizing interrupt requests on behalf of the microprocessor, the microprocessor therefore need not devote significant internal resources to prioritizing the interrupt request signals.

公开(公告)号：HK1063674A1

公开(公告)日：2005-01-07

申请号：HK04106447

申请日：2004-08-27

Applicant: QUALCOMM INC

Inventor： KHAN SAFI ,  YU NICHOLAS K ,  HASQUINE DAVID W ,  FUCHS ROBERT ,  STAFFORD DAVID ,  DHAWAN RAJAT

IPC: G06F20060101 ,  G06F1/08 ,  G06F1/10 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38

公开(公告)号：CA2704892A1

公开(公告)日：2001-06-21

申请号：CA2704892

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G11C16/02 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.