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    Mobile communication device having integrated embedded flash memory and sram
    1.
    发明专利
    Mobile communication device having integrated embedded flash memory and sram 有权
    具有集成嵌入式闪存和SRAM的移动通信设备

    公开(公告)号：JP2012141993A

    公开(公告)日：2012-07-26

    申请号：JP2012024016

    申请日：2012-02-07

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUS-SEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

    IPC: G06F12/06 ,  G06F21/24 ,  G06F12/00 ,  G06F21/00 ,  G06F21/20 ,  G06F21/22 ,  G11C7/24 ,  G11C16/02 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C16/22 ,  G11C2216/22

    Abstract: PROBLEM TO BE SOLVED: To improve access time of flash memory and SRAM and reduce power consumption of an ASIC-based mobile telephone.SOLUTION: The flash memory and SRAM are embedded within an application specific integrated circuit (ASIC) to provide improved access times. The flash memory system includes a flash memory array 130 configured to provide a set of individual flash macros and a flash memory controller 132 for accessing the flash macros. The flash memory controller includes a write-while-reading unit 144, 146 for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers 138, and a password register 140 providing separate passwords for different portions of the flash memory array.

    Abstract translation: 要解决的问题：改善闪存和SRAM的访问时间，并降低基于ASIC的移动电话的功耗。 解决方案：闪存和SRAM嵌入到专用集成电路（ASIC）中，以提供更好的访问时间。 闪存系统包括被配置为提供一组单独的闪存宏的闪存阵列130和用于访问闪存宏的闪存控制器132。 闪速存储器控制器包括写入同时读取单元144,146，用于在同时从另一个闪存宏读取时写入闪存宏中的一个。 闪速存储器控制器还包括可编程等待状态寄存器138和密码寄存器140，为闪存阵列的不同部分提供单独的密码。 版权所有（C）2012，JPO＆INPIT

    Mobile communication device having integrated embedded flash and sram memory
    2.
    发明专利
    Mobile communication device having integrated embedded flash and sram memory 审中-公开
    具有集成嵌入式闪存和SRAM存储器的移动通信设备

    公开(公告)号：JP2012141994A

    公开(公告)日：2012-07-26

    申请号：JP2012024017

    申请日：2012-02-07

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUS-SEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

    IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/02 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C16/22 ,  G11C2216/22

    Abstract: PROBLEM TO BE SOLVED: To provide a flash memory system where a boot loader is swapped into high memory such that other data and programs can be stored within low memory where they can be accessed more expediently.SOLUTION: The flash memory system includes flash memory cells and a flash memory controller 132 provided with means for partitioning the flash memory cells into high and low memory locations. The flash memory cells store a boot loader beginning at a lowest memory address of the flash memory space. The means for partitioning includes means for swapping the high and low memory locations after operations performed by the boot loader have been completed. A memory swap unit 149 is provided for swapping the high and low memory subsequent to the completion of operations performed by the boot loader.

    Abstract translation: 要解决的问题：提供一种闪存系统，其中引导加载器被交换到高存储器中，使得其他数据和程序可以被存储在低内存中，从而可以更方便地访问它们。 闪存系统包括闪存单元和闪速存储器控制器132，闪存控制器132具有用于将闪存单元分成高和低存储器位置的装置。 闪存单元存储从闪存空间的最低存储器地址开始的引导加载程序。 用于分区的装置包括用于在由引导加载器执行的操作已经完成之后交换高和低存储器位置的装置。 提供存储器交换单元149，用于在由引导加载程序执行的操作完成之后交换高和低存储器。 版权所有（C）2012，JPO＆INPIT

    4.
    发明专利
    未知

    公开(公告)号：BR9912991A

    公开(公告)日：2002-01-22

    申请号：BR9912991

    申请日：1999-08-13

    Applicant: QUALCOMM INC

    Inventor： BUTLER BRIAN K ,  YU NICHOLAS K ,  EASTON KENNETH D

    IPC: G06F1/08 ,  G06F1/32 ,  H03L7/00 ,  H04B1/16 ,  H04B7/26 ,  H04L7/02 ,  H04L7/033 ,  H04W52/02 ,  H04Q7/32 ,  G06F1/12

    Abstract: A method and circuit for controlling a mobile station operating in a slotted paging environment. The circuit comprises a low power clock for generating a low frequency clock signal; a clock signal generator for generating a high frequency clock signal; a synchronization logic circuit for synchronizing the low frequency clock signal to the high frequency clock signal; a frequency error estimator for measuring an estimated low frequency clock error; and a sleep controller for removing power from the clock signal generator for the corrected sleep duration value, thereby conserving power between assigned paging slots. During the awake time, the low frequency clock signal is resynchronized to the high frequency clock, thereby correcting for any frequency error in the less accurate low power clock during sleep mode.

    MOBILE COMMUNICATION DEVICE HAVING INTEGRATED EMBEDDED FLASH AND SRAM MEMORY
    5.
    发明专利
    MOBILE COMMUNICATION DEVICE HAVING INTEGRATED EMBEDDED FLASH AND SRAM MEMORY 未知

    公开(公告)号：CA2704894A1

    公开(公告)日：2001-06-21

    申请号：CA2704894

    申请日：2000-12-14

    Applicant: QUALCOMM INC

    Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

    IPC: G06F12/06 ,  G11C16/02 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/06 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

    Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

    DISPOSITIVO DE COMUNICACION MOVIL QUE PRESENTA UNA MEMORIA FLASH Y UNA MEMORIA SRAM INCORPORADAS E INTEGRADAS.
    7.
    发明专利
    DISPOSITIVO DE COMUNICACION MOVIL QUE PRESENTA UNA MEMORIA FLASH Y UNA MEMORIA SRAM INCORPORADAS E INTEGRADAS. 未知

    公开(公告)号：ES2269213T3

    公开(公告)日：2007-04-01

    申请号：ES00986483

    申请日：2000-12-14

    Applicant: QUALCOMM INC

    Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

    IPC: G06F12/00 ,  G06F12/06 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

    Abstract: Sistema de memoria flash (112) que comprende: unas celdas de memoria flash dispuestas como un conjunto de macros flash (130), y unos medios de lectura durante escritura (144, 146) para escribir en una de dichas macros flash, mientras se lee simultáneamente en otra de dichas macros flash; en el que el sistema está conectado a un microprocesador (102) y en el que dichos medios de lectura durante escritura (144, 146) incluyen: unos medios de escritura (146) para escribir las señales recibidas desde el microprocesador a una macro seleccionada de dichas macros flash (130); y caracterizado porque dichos medios de lectura durante escritura incluyen además unos medios de suspensión, sensibles a la recepción de un mandato de lectura del microprocesador dirigido a dicha macro seleccionada de dichas macros flash, para suspender la operación del microprocesador hasta que los medios de escritura (146) hayan finalizado su operación, y para ejecutar el mandato de lectura.

    Mobile communication device having integrated embedded flash and SRAM memory
    8.
    发明授权
    Mobile communication device having integrated embedded flash and SRAM memory 有权
    具有集成嵌入式闪存和SRAM存储器的移动通信设备

    公开(公告)号：US6392925B2

    公开(公告)日：2002-05-21

    申请号：US81818601

    申请日：2001-03-26

    Applicant: QUALCOMM INC

    Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

    IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C7/00

    CPC classification number: G11C16/26 ,  G11C16/22 ,  G11C2216/22

    Abstract: The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory. Thus, portions of flash memory subject to flash memory degradation may be programmed with a higher number of wait states than portions of memory that are not subject to degradation.

    Abstract translation: 闪存和SRAM存储器嵌入到专用集成电路（ASIC）中，以提供改进的访问时间，并且还降低采用ASIC的移动电话的总体功耗。 闪存系统包括被配置为提供一组单独的闪存宏的闪存阵列和用于访问闪存宏的闪存控制器。 闪速存储器控制器包括一个写入单元，用于写入其中一个闪存宏，同时从另一个闪存宏读取。 通过在写入时允许读取，读取操作不需要延迟，直到完成等待写入操作。 闪存控制器还包括可编程等待状态寄存器。 每个等待状态寄存器存储与闪存的一部分相关联的可编程数量的闪存总线等待状态。 因此，存在闪速存储器劣化的闪存的部分可以被编程为具有比没有劣化的存储器部分更多的等待状态。

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