公开(公告)号：DE60030765D1

公开(公告)日：2006-10-26

申请号：DE60030765

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU K ,  KHAN SAFI

IPC: G06F12/06 ,  G11C7/24 ,  G06F12/00 ,  G06F21/00 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：CA2704894A1

公开(公告)日：2001-06-21

申请号：CA2704894

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G11C16/02 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/06 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

公开(公告)号：US6392925B2

公开(公告)日：2002-05-21

申请号：US81818601

申请日：2001-03-26

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C7/00

CPC classification number: G11C16/26 ,  G11C16/22 ,  G11C2216/22

Abstract: The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory. Thus, portions of flash memory subject to flash memory degradation may be programmed with a higher number of wait states than portions of memory that are not subject to degradation.

Abstract translation: 闪存和SRAM存储器嵌入到专用集成电路（ASIC）中，以提供改进的访问时间，并且还降低采用ASIC的移动电话的总体功耗。 闪存系统包括被配置为提供一组单独的闪存宏的闪存阵列和用于访问闪存宏的闪存控制器。 闪速存储器控制器包括一个写入单元，用于写入其中一个闪存宏，同时从另一个闪存宏读取。 通过在写入时允许读取，读取操作不需要延迟，直到完成等待写入操作。 闪存控制器还包括可编程等待状态寄存器。 每个等待状态寄存器存储与闪存的一部分相关联的可编程数量的闪存总线等待状态。 因此，存在闪速存储器劣化的闪存的部分可以被编程为具有比没有劣化的存储器部分更多的等待状态。

公开(公告)号：WO0145106A2

公开(公告)日：2001-06-21

申请号：PCT/US0034216

申请日：2000-12-14

Applicant: QUALCOMM INC

Inventor： JHA SANJAY ,  SIMMONDS STEPHEN ,  ELHUSSEINI JALAL ,  YU NICHOLAS K ,  KHAN SAFI

IPC: G06F12/06 ,  G06F12/00 ,  G06F21/00 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C

CPC classification number: G11C16/26 ,  G11C16/22 ,  G11C2216/22

Abstract: The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

Abstract translation: 闪存和SRAM存储器（112,113）嵌入专用集成电路（ASIC）中以提供改进的访问时间，并且还减少采用ASIC的移动电话的所有功耗。 闪存系统（112）包括被配置为提供一组单独的闪存宏的闪存阵列（130）和用于访问闪存宏的闪存控制器（132）。 闪速存储器控制器包括用于在从另一个闪存宏读取同时从闪存宏中的一个闪存宏写入的写入单元（144,146）。 闪存控制器还包括可编程等待状态寄存器（138）和密码寄存器（140），为闪存阵列的不同部分提供单独的密码。 提供存储器交换单元（149），用于在完成由引导加载程序执行的操作之后交换高和低存储器。 公开了方法和设备实现。