公开(公告)号：WO2017136099A2

公开(公告)日：2017-08-10

申请号：PCT/US2017/012514

申请日：2017-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： ALAVOINE, Olivier ,  LEE, Sejoong ,  KAZI, Tauseef ,  BOOTH, Simon ,  REGINI, Edoardo ,  JAKUSHOKAS, Renatas ,  PATODIA, Saurabh ,  GEMAR, Jeffrey ,  LO, Haw-Jing ,  CHAMARTY, Vinod ,  ANDREEV, Boris ,  SHEN, Tao ,  BHASKARA, Aravind ,  WANG, Wenbiao ,  MOLLOY, Stephen

CPC classification number: G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Abstract translation: 各种方面包括用于管理计算设备上的存储器子系统的方法。 各种方面方法可以包括确定强制计算设备上的存储器子系统进入低功率模式的时间段，在确定的时间段期间禁止对存储器子系统的存储器访问请求，迫使存储器子系统进入低功率模式 所确定的时间周期，并且响应于所确定的时间段的期满，在所确定的时间段期间向存储器子系统执行存储器访问请求。

公开(公告)号：WO2012054754A1

公开(公告)日：2012-04-26

申请号：PCT/US2011/057142

申请日：2011-10-20

Applicant: QUALCOMM INCORPORATED ,  DUROIU, Cristian ,  GANASAN, Jaya Prakash Subramaniam ,  CHAMARTY, Vinod ,  SCHAFFER, Mark Michael ,  STUBBS, Joshua H. ,  GIBSON, Robert N. ,  TIRI, Kris ,  KHAN, Moinul H. ,  RYCHLIK, Bohuslav ,  GADELRAB, Serag ,  BOOTH, Simon

Inventor： DUROIU, Cristian ,  GANASAN, Jaya Prakash Subramaniam ,  CHAMARTY, Vinod ,  SCHAFFER, Mark Michael ,  STUBBS, Joshua H. ,  GIBSON, Robert N. ,  TIRI, Kris ,  KHAN, Moinul H. ,  RYCHLIK, Bohuslav ,  GADELRAB, Serag ,  BOOTH, Simon

IPC: G06F13/362

CPC classification number: G06F13/362 ,  Y02D10/14

Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Abstract translation: 公开了用于基于健康信息在通信总线上仲裁总线事务的设备，系统，方法和计算机可读介质。 主设备的健康信息可用于调整主设备总线事务的优先级，以满足主设备的服务质量要求。 在一个实施例中，总线互连被提供和配置为将总线事务从多个主设备中的任一个传送到耦合总线互连的从设备。 总线互连还被配置为将多个主设备中的每一个的健康信息映射到虚拟优先级空间中。 总线互连还被配置为将虚拟优先级空间转换为多个主设备中的每一个的物理优先级。 总线互连还被配置为基于多个主设备的物理优先级来仲裁多个主设备的总线事务。

公开(公告)号：EP3411775B1

公开(公告)日：2019-12-25

申请号：EP17701232.5

申请日：2017-01-06

Applicant: Qualcomm Incorporated

Inventor： ALAVOINE, Olivier ,  LEE, Sejoong ,  KAZI, Tauseef ,  BOOTH, Simon ,  REGINI, Edoardo ,  JAKUSHOKAS, Renatas ,  PATODIA, Saurabh ,  GEMAR, Jeffrey ,  LO, Haw-Jing ,  CHAMARTY, Vinod ,  ANDREEV, Boris ,  SHEN, Tao ,  BHASKARA, Aravind ,  WANG, Wenbiao ,  MOLLOY, Stephen

IPC: G06F1/32

公开(公告)号：EP3213203A1

公开(公告)日：2017-09-06

申请号：EP15801523.0

申请日：2015-10-15

Applicant: Qualcomm Incorporated

Inventor： DUROIU, Cristian ,  CHAMARTY, Vinod ,  GADELRAB, Serag ,  DROP, Michael ,  SINHA, Pooja ,  LIU, Ruolong ,  CHAPARRO, John, Daniel ,  CUPPU, Vinodh, Ramesh ,  LEE, Joseph, Schweiray ,  KUAN, Johnny, Jone, Wai ,  CHOW, Paul ,  VOOTUKURU, Anil ,  MITTER, Vinay

IPC: G06F9/50

CPC classification number: H04L47/783 ,  G06F9/50 ,  G06F9/5016 ,  G06F9/505 ,  H04L47/72

Abstract: A method and system for managing safe downtime of shared resources within a portable computing device are described. The method may include determining a tolerance for a downtime period for an unacceptable deadline miss element of the portable computing device. Next, the determined tolerance for the downtime period may be transmitted to quality-of-service (“QoS”) controller. The QoS controller may determine if the tolerance for the downtime period needs to be adjusted. The QoS controller may receive a downtime request from one or more shared resources of the portable computing device. The QoS controller may determine if the downtime request needs to be adjusted. Next, the QoS controller may select a downtime request for execution and then identify which one or more unacceptable deadline miss elements of the portable computing device that are impacted by the selected downtime request.

Abstract translation: 描述了用于管理便携式计算设备内的共享资源的安全停机时间的方法和系统。 该方法可以包括确定便携式计算设备的不可接受的期限未命中元件的停机时间段的容限。 接下来，所确定的停机时间段的容差可以被传送给服务质量（“QoS”）控制器。 QoS控制器可以确定是否需要调整停机时间段的容限。 QoS控制器可以从便携式计算设备的一个或多个共享资源接收停机请求。 QoS控制器可以确定是否需要调整停机时间请求。 接下来，QoS控制器可以选择用于执行的停机时间请求，然后识别受选择的停机时间请求影响的便携式计算设备的哪一个或多个不可接受的期限未命中元件。

公开(公告)号：EP3414666B1

公开(公告)日：2020-11-04

申请号：EP17704117.5

申请日：2017-01-14

Applicant: Qualcomm Incorporated

Inventor： GADELRAB, Serag ,  VARIA, Meghal ,  WURJANTARA, Wisnu ,  SUNG, Clara Ka Wah ,  STERNBERG, Mark ,  ANDRIJANIC, Vladan ,  RINALDI, Antonio ,  CHAMARTY, Vinod ,  SINHA, Pooja ,  WANG, Tao ,  GRUBER, Andrew

IPC: G06F13/16

公开(公告)号：EP3170085A1

公开(公告)日：2017-05-24

申请号：EP15734019.1

申请日：2015-06-25

Applicant: Qualcomm Incorporated

Inventor： PALACHARLA, Subbarao ,  KHAN, Moinul ,  ARTIERI, Alain ,  BHOLE, Kedar ,  CHAMARTY, Vinod ,  CHAURASIA, Pankaj ,  SANKURATRI, Raghu

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

Abstract translation: 方面包括计算设备，系统，和用于分割由多组和方式的系统的高速缓存成组分缓存的方法。 一种系统，高速缓冲存储器控制器可以管理组件的高速缓存和管理对组件的高速缓存。 系统高速缓存存储器控制器可以接收指定部件缓存标识系统缓存的访问请求，并与记录在组件缓存配置表进行相关组件缓存标识的性状与匹配部件缓存标识。 组件的高速缓存的性状可以包括一组移性状，设定偏移性状，和目标的方式，这可以在系统缓存定义组件的高速缓存的位置。 因此，该系统的高速缓冲存储器控制器可接收的物理地址为系统中的高速缓存访​​问请求的高速缓存系统，确定性矿索引模式为组件高速缓存，和用于该组件的高速缓存翻译的物理地址。

公开(公告)号：EP3170085B1

公开(公告)日：2018-08-15

申请号：EP15734019.1

申请日：2015-06-25

Applicant: Qualcomm Incorporated

Inventor： PALACHARLA, Subbarao ,  KHAN, Moinul ,  ARTIERI, Alain ,  BHOLE, Kedar ,  CHAMARTY, Vinod ,  CHAURASIA, Pankaj ,  SANKURATRI, Raghu

IPC: G06F12/0895 ,  G06F12/084 ,  G06F12/0893 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

公开(公告)号：EP3170084B1

公开(公告)日：2018-06-06

申请号：EP15734017.5

申请日：2015-06-25

Applicant: Qualcomm Incorporated

Inventor： PALACHARLA, Subbarao ,  KHAN, Moinul ,  ARTIERI, Alain ,  BHOLE, Kedar ,  CHAMARTY, Vinod ,  LI, Yanru ,  SANKURATRI, Raghu ,  PATSILARAS, George ,  THIRUNAGARI, Pavan Kumar ,  TURNER, Andrew Edmund ,  WOO, Jeong-Ho

IPC: G06F12/0895 ,  G06F12/084 ,  G06F12/0893 ,  G06F9/50

CPC classification number: G06F12/0893 ,  G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0888 ,  G06F12/0895 ,  G06F17/30902 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6042 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

公开(公告)号：EP3170084A1

公开(公告)日：2017-05-24

申请号：EP15734017.5

申请日：2015-06-25

Applicant: Qualcomm Incorporated

Inventor： PALACHARLA, Subbarao ,  KHAN, Moinul ,  ARTIERI, Alain ,  BHOLE, Kedar ,  CHAMARTY, Vinod ,  LI, Yanru ,  SANKURATRI, Raghu ,  PATSILARAS, George ,  THIRUNAGARI, Pavan Kumar ,  TURNER, Andrew Edmund ,  WOO, Jeong-Ho

IPC: G06F12/08 ,  G06F9/50

CPC classification number: G06F12/0893 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0895 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6042 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

Abstract translation: 方面包括计算设备，系统和方法，用于动态地划分由集和方法的系统的高速缓存成组分缓存。 一种系统，高速缓冲存储器控制器可以管理组件的高速缓存和管理对组件的高速缓存。 系统高速缓存存储器控制器可以接收在系统缓存对应于与所述请求的组件标识符高速缓存相关联的高速缓存组件的高速缓存系统的访问请求和储备位置。 在系统缓存预留的位置可以由请求的客户端激活系统中的高速缓存使用的位置，并且因此可以防止其他客户机使用在系统缓存的保留位置。 释放系统缓存中的位置可以停用系统缓存的位置，并允许其他客户机使用。 客户端系统中的高速缓存保留位置可以改变它的高速缓存部件中的保留位置的量。

公开(公告)号：EP2630578A1

公开(公告)日：2013-08-28

申请号：EP11776304.5

申请日：2011-10-20

Applicant: Qualcomm Incorporated

Inventor： DUROIU, Cristian ,  GANASAN, Jaya Prakash Subramaniam ,  CHAMARTY, Vinod ,  SCHAFFER, Mark Michael ,  STUBBS, Joshua H. ,  GIBSON, Robert N. ,  TIRI, Kris ,  KHAN, Moinul H. ,  RYCHLIK, Bohuslav ,  GADELRAB, Serag ,  BOOTH, Simon

IPC: G06F13/362

CPC classification number: G06F13/362 ,  Y02D10/14

Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.