公开(公告)号：WO2014070264A1

公开(公告)日：2014-05-08

申请号：PCT/US2013/051231

申请日：2013-07-19

Applicant: QUALCOMM INCORPORATED

Inventor： LO, Haw-Jing ,  TAHA, Ali ,  CHUN, Dexter T.

IPC: G06F1/32

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/023 ,  Y02D10/14 ,  Y02D50/20

Abstract: Various embodiments of methods and systems for hardware (HW) based dynamic memory management in a portable computing device (PCD) are disclosed. One exemplary method includes generating a lookup table (LUT) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

Abstract translation: 公开了在便携式计算设备（PCD）中基于硬件（HW）的动态存储器管理的方法和系统的各种实施例。 一种示例性方法包括生成查找表（LUT）以跟踪位于易失性存储器的多个部分上的每个存储器页面。 更新LUT中的记录以跟踪数据位置。 当PCD进入睡眠状态以节省能量时，可以查询LUT以确定易失性存储器（例如，上部存储体）的第一部分中的哪些特定存储器页面包含数据内容以及易失性存储器的第二部分中的哪些页面 例如，较低的银行）可用于接收内容。 基于该查询，数据在上部存储器页面中的位置是已知的，并且可以被快速迁移到被识别用于接收数据的下部的存储器页面中。

公开(公告)号：WO2015042469A1

公开(公告)日：2015-03-26

申请号：PCT/US2014/056659

申请日：2014-09-19

Applicant: QUALCOMM INCORPORATED

Inventor： LO, Haw-Jing ,  CHUN, Dexter

IPC: G06F1/32

CPC classification number: G06F13/4018 ,  G06F1/3253 ,  G06F1/3275 ,  G06F13/1678 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.

Abstract translation: 公开了用于节省存储器系统中的功耗的系统和方法。 一种这样的系统包括DRAM存储器系统和片上系统（SoC）。 SoC通过存储器总线耦合到DRAM存储器系统。 SoC包括用于处理来自一个或多个存储器客户端的用于访问DRAM存储器系统的存储器请求的一个或多个存储器控制器。 一个或多个存储器控制器被配置为通过动态地调整存储器总线的总线宽度来选择性地节省存储器功耗。

公开(公告)号：WO2017136099A3

公开(公告)日：2017-08-10

申请号：PCT/US2017/012514

申请日：2017-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： ALAVOINE, Olivier ,  LEE, Sejoong ,  KAZI, Tauseef ,  BOOTH, Simon ,  REGINI, Edoardo ,  JAKUSHOKAS, Renatas ,  PATODIA, Saurabh ,  GEMAR, Jeffrey ,  LO, Haw-Jing ,  CHAMARTY, Vinod ,  ANDREEV, Boris ,  SHEN, Tao ,  BHASKARA, Aravind ,  WANG, Wenbiao ,  MOLLOY, Stephen

IPC: G06F1/32

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

公开(公告)号：WO2015134337A1

公开(公告)日：2015-09-11

申请号：PCT/US2015/018203

申请日：2015-02-28

Applicant: QUALCOMM INCORPORATED

Inventor： IRANLI, Ali ,  KHAN, Moinul ,  LO, Haw-Jing

IPC: G06F1/32

CPC classification number: G06T1/60 ,  G06F1/3218 ,  G06F1/3265 ,  G06F1/3275 ,  G09G2330/022 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/153 ,  Y02D50/20

Abstract: Systems, methods, and computer programs are disclosed for reducing power consumption for static image display refresh in a dynamic random access memory (DRAM) memory system. One such method comprises: prefetching static image frame content from a DRAM memory device into a system cache; during a static display refresh operation, a display processor reads the static image frame content from the system cache while the DRAM memory device is in a power-saving, self-refresh state; and the display processor feeding the static image frame content to a mobile display.

Abstract translation: 公开了用于降低动态随机存取存储器（DRAM）存储器系统中静态图像显示刷新的功耗的系统，方法和计算机程序。 一种这样的方法包括：将静态图像帧内容从DRAM存储器设备预取到系统高速缓存中; 在静态显示刷新操作期间，显示处理器在DRAM存储器件处于省电自刷新状态的同时从系统高速缓存读取静态图像帧内容; 并且显示处理器将静态图像帧内容馈送到移动显示器。

公开(公告)号：WO2014186229A1

公开(公告)日：2014-11-20

申请号：PCT/US2014/037525

申请日：2014-05-09

Applicant: QUALCOMM INCORPORATED

Inventor： LO, Haw-Jing ,  CHUN, Dexter

IPC: G11C11/406 ,  G11C11/4072 ,  G11C7/04 ,  G06F13/16

CPC classification number: G11C11/40622 ,  G11C7/04 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40626 ,  G11C11/4072

Abstract: Methods and devices for refreshing a dynamic memory device, (e.g., DRAM) to eliminate unnecessary page refresh operations. A value in a lookup table for the page may indicate whether valid data including all zeros is present in the page. When the page includes valid data of all zeros, the lookup table value may be set so that refresh, memory read, write and clear accesses of the page may be inhibited and a valid value may be returned. A second lookup table may contain a second value indicating whether a page has been accessed by a page read or write during the page refresh interval. A page refresh, by issuing an ACT -PRE command pair, and a page address may be performed according to the page refresh interval when the second value indicates that page access has not occurred.

Abstract translation: 用于刷新动态存储设备（例如，DRAM）以消除不必要的页面刷新操作的方法和设备。 该页面的查找表中的值可以指示页面中是否存在包括全部零的有效数据。 当页面包括全零的有效数据时，可以设置查找表值，使得可以禁止页面的刷新，存储器读取，写入和清除访问，并且可以返回有效值。 第二查找表可以包含指示在页面刷新间隔期间页面是否被页面读取或写入访问的第二值。 当第二个值指示没有发生页面访问时，可以根据页面刷新间隔来执行通过发出ACT -PRE命令对的页面刷新和页面地址。

公开(公告)号：WO2016081322A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/060740

申请日：2015-11-13

Applicant: QUALCOMM INCORPORATED

Inventor： QUACH, Nhon Toai ,  DEEPAK, Virat ,  ARIAS, Oscar Cabral ,  LI, Yanru ,  LO, Haw-Jing ,  DROP, Michael ,  PINNAMARAJU DURGA, Venkata Narayana ,  KHAN, Moinul

IPC: G06F1/32 ,  H03M7/30

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F2212/1028 ,  G06F2212/401 ,  G11C11/4074 ,  G11C11/409 ,  H03M7/30 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.

Abstract translation: 公开了用于减少便携式计算设备中的易失性存储器待机功率的系统和方法的各种实施例。 一种这样的方法包括接收对易失性存储器设备进入待机功率模式的请求。 确定一个或多个压缩参数以压缩存储在易失性存储器件的多个存储体中的内容。 存储的内容基于一个或多个压缩参数被压缩以释放多个存储体中的至少一个存储体。 该方法禁用在待机功率模式期间由压缩释放的多个组中的一个或多个的至少一部分的自刷新。

公开(公告)号：WO2015106145A1

公开(公告)日：2015-07-16

申请号：PCT/US2015/010883

申请日：2015-01-09

Applicant: QUALCOMM INCORPORATED

Inventor： MONDAL, Mriganka ,  LO, Haw-Jing

IPC: G11C11/4096 ,  G11C7/10

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0673 ,  G06F12/0607 ,  G06F13/1626 ,  G06F2212/652 ,  G11C7/1042 ,  G11C7/1072 ,  G11C7/1075 ,  G11C11/4096 ,  Y02D10/14

Abstract: Systems, methods, and computer programs are disclosed for managing access requests to a DRAM memory device (104). One embodiment includes receiving memory access pattern data (116) for at least one of a plurality of memory clients (110) prior to a corresponding memory transaction with a DRAM memory device (104). Next, it is determined (114), based on the received memory access pattern data (116), that a future transaction of a first of the plurality of memory clients (110) may create a future page conflict with a current transaction of a second of the plurality of memory clients (110). The future page conflict is then resolved by interleaving access to an associated bank (106) in the DRAM memory device (104) by the first and second memory clients (110) according to the received memory access pattern data (116).

Abstract translation: 公开了用于管理对DRAM存储器件（104）的访问请求的系统，方法和计算机程序。 一个实施例包括在与DRAM存储器设备（104）进行相应的存储器处理之前，为多个存储器客户端（110）中的至少一个接收存储器访问模式数据（116）。 接下来，基于所接收的存储器访问模式数据（116）确定（114）多个存储器客户端（110）中的第一个存储器客户端（110）的未来事务可能与第二个存储器访问模式数据 的多个存储器客户端（110）。 然后，根据接收到的存储器访问模式数据（116），通过第一和第二存储器客户端（110）对DRAM存储器设备（104）中的相关联存储体（106）的访问进行交织来解决未来页面冲突。

公开(公告)号：WO2011085323A3

公开(公告)日：2011-07-14

申请号：PCT/US2011/020701

申请日：2011-01-10

Applicant: QUALCOMM INCORPORATED ,  THOMSON, Steven S. ,  IRANLI, Ali ,  DROP, Michael J. ,  CUPPU, Vinodh R. ,  CHUN, Christopher Kong Yee ,  XUE, Tao ,  LO, Haw-Jing ,  KHAN, Moinul, H.

Inventor： THOMSON, Steven S. ,  IRANLI, Ali ,  DROP, Michael J. ,  CUPPU, Vinodh R. ,  CHUN, Christopher Kong Yee ,  XUE, Tao ,  LO, Haw-Jing ,  KHAN, Moinul, H.

IPC: G06F1/32

Abstract: A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings.

公开(公告)号：EP2915019B1

公开(公告)日：2017-04-19

申请号：EP13745935.0

申请日：2013-07-19

Applicant: Qualcomm Incorporated

Inventor： LO, Haw-Jing ,  TAHA, Ali ,  CHUN, Dexter T.

IPC: G06F1/32

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/023 ,  Y02D10/14 ,  Y02D50/20

Abstract: Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

公开(公告)号：EP3047352A1

公开(公告)日：2016-07-27

申请号：EP14784149.8

申请日：2014-09-19

Applicant: Qualcomm Incorporated

Inventor： LO, Haw-Jing ,  CHUN, Dexter

IPC: G06F1/32

CPC classification number: G06F13/4018 ,  G06F1/3253 ,  G06F1/3275 ,  G06F13/1678 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.