BANDWIDTH/RESOURCE MANAGEMENT FOR MULTITHREADED PROCESSORS
    2.
    发明申请
    BANDWIDTH/RESOURCE MANAGEMENT FOR MULTITHREADED PROCESSORS 审中-公开
    多重处理器的宽带/资源管理

    公开(公告)号:WO2016195851A1

    公开(公告)日:2016-12-08

    申请号:PCT/US2016/029530

    申请日:2016-04-27

    Abstract: Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.

    Abstract translation: 系统和方法涉及在包括两个或多个处理线程的多线程处理器中管理共享资源。 确定两个或更多个线程的危险水平,其中线程的危险等级基于线程由于不可用的共享资源而遇到期限的潜在故障。 还确定与两个或更多个线程相关联的优先级,其中对于不能达到期限的线程而言,优先级高于不能接受的线程,并且对于不满足截止期限的线程,优先级较低。 至少基于与两个或多个线程相关联的两个或多个线程的确定的危险等级和优先级,来调度两个或更多个线程。

    SYSTEM AND METHOD FOR UNIFORM INTERLEAVING OF DATA ACROSS A MULTIPLE-CHANNEL MEMORY ARCHITECTURE WITH ASYMMETRIC STORAGE CAPACITY
    7.
    发明申请
    SYSTEM AND METHOD FOR UNIFORM INTERLEAVING OF DATA ACROSS A MULTIPLE-CHANNEL MEMORY ARCHITECTURE WITH ASYMMETRIC STORAGE CAPACITY 审中-公开
    通过具有不对称存储容量的多通道存储器架构来均匀地交换数据的系统和方法

    公开(公告)号:WO2015051201A1

    公开(公告)日:2015-04-09

    申请号:PCT/US2014/058946

    申请日:2014-10-03

    CPC classification number: G06F12/0607

    Abstract: Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.

    Abstract translation: 公开了跨物理通道具有不均匀存储容量的存储器空间的物理信道的均匀交织的系统和方法。 交织器布置成与一个或多个处理器和系统存储器通信。 交织器识别由存储器通道支持的存储器空间中的位置,并响应于定义具有期望存储容量的虚拟扇区的逻辑。 响应于访问存储器空间的请求,交织器跨虚拟扇区均匀地访问非对称存储容量。

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