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    CLASSIFIER FOR RADIO FREQUENCY FRONT-END (RFFE) DEVICES
    11.
    发明申请
    CLASSIFIER FOR RADIO FREQUENCY FRONT-END (RFFE) DEVICES 审中-公开
    无线电频率前端（RFFE）设备分类器

    公开(公告)号：WO2013138005A1

    公开(公告)日：2013-09-19

    申请号：PCT/US2013/025755

    申请日：2013-02-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： GRUBER, Hans Georg ,  O'SHEA, Helena Deirdre ,  HOLENSTEIN, Christian

    IPC: H04B1/00 ,  H04B1/40 ,  H04L29/08 ,  H04L12/24 ,  H04L12/403

    CPC classification number: H04B1/40 ,  H04B1/005 ,  H04L12/403 ,  H04L41/0896

    Abstract: A method for classifying radio frequency front-end (RFFE) devices. The method includes enumerating a radio frequency front-end (RFFE) slave device according to at least one classifier bit within the RFFE slave device. The method also includes adjusting an RFFE control interface of an RFFE master device according to slave device configuration information determined from the at least one classifier bit within the RFFE slave device.

    Abstract translation: 一种用于对射频前端（RFFE）设备进行分类的方法。 该方法包括根据RFFE从设备中的至少一个分类器位置列举射频前端（RFFE）从设备。 该方法还包括根据从RFFE从设备中的至少一个分类器位确定的从设备配置信息调整RFFE主设备的RFFE控制接口。

    SINGLE-CHIP SIGNAL SPLITTING CARRIER AGGREGATION RECEIVER ARCHITECTURE
    12.
    发明申请
    SINGLE-CHIP SIGNAL SPLITTING CARRIER AGGREGATION RECEIVER ARCHITECTURE 审中-公开
    单芯片信号分离载波聚合接收机架构

    公开(公告)号：WO2013131051A1

    公开(公告)日：2013-09-06

    申请号：PCT/US2013/028742

    申请日：2013-03-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： GUDEM, Prasad Srinivasa Siva ,  SAHOTA, Gurkanwal Singh ,  CHANG, Li-Chung ,  HOLENSTEIN, Christian ,  BOSSU, Frederic

    IPC: H04B1/00 ,  H04B1/48

    CPC classification number: H04B1/0057 ,  H04B7/04

    Abstract: A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path.

    Abstract translation: 描述了被配置为接收多载波信号的无线通信设备。 无线通信设备包括单芯片信号分离载波聚合接收机架构。 单芯片信号分离载波聚合接收机架构包括主天线，辅助天线和收发芯片。 单芯片信号分离载波聚合接收机架构重用同步混合双接收机路径。

    SYSTEMS AND METHODS FOR ADJUSTING THE GAIN OF A RECEIVER THROUGH A GAIN TUNING NETWORK
    13.
    发明申请
    SYSTEMS AND METHODS FOR ADJUSTING THE GAIN OF A RECEIVER THROUGH A GAIN TUNING NETWORK 审中-公开
    通过增益网络调整接收器的增益的系统和方法

    公开(公告)号：WO2010017137A2

    公开(公告)日：2010-02-11

    申请号：PCT/US2009/052583

    申请日：2009-08-03

    Applicant: QUALCOMM INCORPORATED ,  TASIC, Aleksandar ,  HOLENSTEIN, Christian ,  DENG, Junxiong

    Inventor： TASIC, Aleksandar ,  HOLENSTEIN, Christian ,  DENG, Junxiong

    IPC: H03G1/00 ,  H03G3/30

    CPC classification number: H03G3/3052

    Abstract: A circuit is described. The circuit includes a low noise amplifier (LNA), a passive switching core (PSC), a transimpedance amplifier filter (TIA-filter) and a degenerative-impedance gain-tuning network (Zdeg network) having a first Zdeg network input lead, a second Zdeg network input lead, a first Zdeg network output lead and a second Zdeg network output lead, wherein the first Zdeg network input lead is coupled to a first output lead of the LNA and the second Zdeg network input lead is coupled to a second output lead of the LNA, and wherein the first Zdeg network output lead is coupled to a first signal input lead of the PSC and the second Zdeg network output lead is coupled to a second signal input lead of the PSC. The LNA, the Zdeg network, the PSC, and the TIA-filter together form a receiver. A receiver gain is adjusted by the Zdeg network.

    Abstract translation: 描述电路。 该电路包括具有第一Zdeg网络输入引线的低噪声放大器（LNA），无源开关核心（PSC），跨阻抗放大器滤波器（TIA滤波器）和退化阻抗增益调谐网络（Zdeg网络） 第二Zdeg网络输入引线，第一Zdeg网络输出引线和第二Zdeg网络输出引线，其中第一Zdeg网络输入引线耦合到LNA的第一输出引线，而第二Zdeg网络输入引线耦合到第二输出 LNA的引线，并且其中第一Zdeg网络输出引线耦合到PSC的第一信号输入引线，并且第二Zdeg网络输出引线耦合到PSC的第二信号输入引线。 LNA，Zdeg网络，PSC和TIA滤波器一起形成接收器。 接收机增益由Zdeg网络调整。

    DC OFFSET CANCELLATION CIRCUIT FOR A RECEIVER
    14.
    发明申请
    DC OFFSET CANCELLATION CIRCUIT FOR A RECEIVER 审中-公开
    用于接收器的DC偏移消除电路

    公开(公告)号：WO2007038782A1

    公开(公告)日：2007-04-05

    申请号：PCT/US2006/038534

    申请日：2006-09-28

    Applicant: QUALCOMM INCORPORATED ,  SUN, Runhua ,  HOLENSTEIN, Christian ,  JAFFEE, James

    Inventor： SUN, Runhua ,  HOLENSTEIN, Christian ,  JAFFEE, James

    IPC: H03D3/00

    CPC classification number: H03D3/008

    Abstract: Techniques for cancelling DC offset are described. A DC offset cancellation circuit in a receiver cancels DC offsets caused by leaked LO (local oscillator) signals from a LO signal generator. The receiver first calibrates itself by using the DC offset cancellation circuit during a transmit mode. During the calibration, the DC offset cancellation circuit stores the DC offset voltage signal caused by the leaked LO signals. During a receiving mode when the receiver is receiving a signal, the receiver subtracts the stored DC offset voltage signal from the received signal to cancel the DC offsets caused by leaked LO signals.

    Abstract translation: 描述了消除DC偏移的技术。 接收器中的DC偏移消除电路消除由LO信号发生器泄漏的LO（本地振荡器）信号引起的DC偏移。 接收机首先通过在发送模式期间使用DC偏移消除电路进行自校准。 在校准期间，DC偏移消除电路存储由泄露的LO信号引起的DC偏移电压信号。 在接收器接收信号的接收模式期间，接收机从接收信号中减去存储的直流失调电压信号，以消除由泄露的LO信号引起的直流偏移。

    DIRECT CURRENT OFFSET CANCELLATION FOR MOBILE STATION MODEMS USING DIRECT CONVERSION
    15.
    发明申请
    DIRECT CURRENT OFFSET CANCELLATION FOR MOBILE STATION MODEMS USING DIRECT CONVERSION 审中-公开
    使用直接转换的移动站模式的直接电流消除

    公开(公告)号：WO2003088606A2

    公开(公告)日：2003-10-23

    申请号：PCT/US2003/011070

    申请日：2003-04-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： HOLENSTEIN, Christian ,  KANG, Inyup ,  SEVERSON, Matthew

    IPC: H04L25/06

    CPC classification number: H04L25/061 ,  H04B1/30

    Abstract: A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.

    Abstract translation: 一种具有直接转换结构的移动台调制解调器的DC偏移消除系统和方法。 本发明是快速获取DC偏移消除块，其提供快速和准确的DC偏移估计和消除技术以支持直接转换架构。 快速获取DC偏移消除块结合了四种机制，通过增加高通环路带宽和调整基带上的直流偏移电平，快速获取和消除上电，温度变化，接收机频率变化和增益设置变化后的直流偏移估计。 在大部分去除DC偏移之后，降低高通环路带宽以微调先前的估计，并消除由于接收机自混合产物引起的DC偏移的任何小的变化。

    ANTENNA INTERFACE CIRCUITS FOR CARRIER AGGREGATION ON MULTIPLE ANTENNAS
    16.
    发明申请
    ANTENNA INTERFACE CIRCUITS FOR CARRIER AGGREGATION ON MULTIPLE ANTENNAS 审中-公开
    天线接口电路用于多个天线的载波聚合

    公开(公告)号：WO2014005061A1

    公开(公告)日：2014-01-03

    申请号：PCT/US2013/048657

    申请日：2013-06-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： WEISSMAN, Haim M. ,  MANSOUR, Rimon E. ,  HOLENSTEIN, Christian

    IPC: H04B1/00

    CPC classification number: H04B1/0064 ,  H04B7/0404

    Abstract: Techniques for supporting data transmission and reception on multiple bands for carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes first and second antenna interface circuits coupled to first and second antennas, respectively. The first antenna interface circuit includes a first transmit (TX) filter for a first band, which may be part of a first triplexer or duplexer. The first TX filter filters a first radio frequency (RF) signal prior to transmission via the first antenna. The second antenna interface circuit includes a second TX filter for a second band, which may be part of a second triplexer or duplexer. The second TX filter filters a second RF signal prior to transmission via the second antenna. The first and second RF signals may be transmitted simultaneously on the first and second bands for carrier aggregation.

    Abstract translation: 公开了用于支持用于载波聚合的多个频带上的数据发送和接收的技术。 在示例性设计中，装置（例如，无线装置）分别包括耦合到第一和第二天线的第一和第二天线接口电路。 第一天线接口电路包括用于第一频带的第一发射（TX）滤波器，其可以是第一三工器或双工器的一部分。 第一TX滤波器在经由第一天线传输之前对第一射频（RF）信号进行滤波。 第二天线接口电路包括用于第二频带的第二TX滤波器，其可以是第二三工器或双工器的一部分。 第二TX滤波器在经由第二天线传输之前对第二RF信号进行滤波。 第一和第二RF信号可以在第一和第二频带上同时传输，用于载波聚合。

    WIRELESS DEVICE WITH FILTERS TO SUPPORT CO-EXISTENCE IN ADJACENT FREQUENCY BANDS
    17.
    发明申请
    WIRELESS DEVICE WITH FILTERS TO SUPPORT CO-EXISTENCE IN ADJACENT FREQUENCY BANDS 审中-公开
    带滤波器的无线设备支持相邻频段中的共存

    公开(公告)号：WO2013126804A1

    公开(公告)日：2013-08-29

    申请号：PCT/US2013/027470

    申请日：2013-02-22

    Applicant: QUALCOMM INCORPORATED

    Inventor： LANE, Mark, Vernon ,  LEE, Chang-Ho ,  HOLENSTEIN, Christian ,  RANJAN, Mahim ,  SAMPATH, Praveen-Kumar ,  BOSSU, Frederic ,  VERMA, Sumit ,  SAMPSON, Wesley, Alan

    IPC: H04B1/04 ,  H04W88/06

    CPC classification number: H04B1/0458 ,  H04B1/04 ,  H04B1/0475

    Abstract: Techniques for using a narrow filter located before a power amplifier to reduce interference in an adjacent frequency band are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes the narrow filter and the power amplifier. The narrow filter is for a first frequency band (e.g., Band 40) and has a first bandwidth that is more narrow than the first frequency band. The narrow filter receives and filters an input radio frequency (RF) signal and provides a filtered RF signal. The power amplifier receives and amplifies the filtered RF signal and provides an amplified RF signal. The apparatus may further include a full filter for the first frequency band and located after the power amplifier. The full filter receives and filters the amplified RF signal and provides an output RF signal when it is selected for use.

    Abstract translation: 公开了使用位于功率放大器之前的窄滤波器来减少相邻频带中的干扰的技术。 在示例性设计中，装置（例如，无线装置）包括窄滤波器和功率放大器。 窄滤波器用于第一频带（例如，频带40），并且具有比第一频带更窄的第一带宽。 窄滤波器接收并过滤输入射频（RF）信号并提供滤波后的RF信号。 功率放大器接收并放大经滤波的RF信号并提供放大的RF信号。 该装置还可以包括用于第一频带并位于功率放大器之后的全滤波器。 全滤波器接收并过滤放大的RF信号，并在选择使用时提供输出RF信号。

    SYSTEMS AND METHODS FOR PRODUCING A PREDETERMINED OUTPUT IN A SEQUENTIAL CIRCUIT DURING POWER ON
    19.
    发明申请
    SYSTEMS AND METHODS FOR PRODUCING A PREDETERMINED OUTPUT IN A SEQUENTIAL CIRCUIT DURING POWER ON 审中-公开
    在通电期间在顺序电路中生成预测输出的系统和方法

    公开(公告)号：WO2010132875A1

    公开(公告)日：2010-11-18

    申请号：PCT/US2010/035084

    申请日：2010-05-17

    Applicant: QUALCOMM INCORPORATED ,  BELLUR, Kashyap, R. ,  DAVIERWALLA, Anosh, B. ,  HOLENSTEIN, Christian

    Inventor： BELLUR, Kashyap, R. ,  DAVIERWALLA, Anosh, B. ,  HOLENSTEIN, Christian

    IPC: H03K19/00 ,  H03K19/0185

    CPC classification number: H03K19/0013 ,  H03K17/22 ,  H03K19/018521

    Abstract: An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage.

    Abstract translation: 公开了一种被配置为在通电期间在顺序电路中产生预定输出的集成电路。 集成电路包括耦合到一个或多个内部节点的一个或多个电容器。 如果电源节点处的电压以一段时间或更快的速度上升到设定电压，则一个或多个电容器对内部节点进行充电。 集成电路还包括耦合到电源节点的第一晶体管。 当电源节点上的电压上升到设定电压时，第一晶体管产生对一个或多个内部节点充电的泄漏电流，不会比时间段更快。 集成电路还包括输出节点。 输出节点上的逻辑值基于充电内部节点上的逻辑值，当时序电路的输入信号不起作用并且电源节点上的电压处于设定电压时。

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