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    POWER MANAGEMENT FOR MULTIPLE-CHIPLET SYSTEMS
    1.
    发明申请
    POWER MANAGEMENT FOR MULTIPLE-CHIPLET SYSTEMS 审中-公开

    公开(公告)号：WO2022271418A1

    公开(公告)日：2022-12-29

    申请号：PCT/US2022/031547

    申请日：2022-05-31

    Applicant: QUALCOMM INCORPORATED

    Inventor： KAKKIRENI, Prashanth Kumar ,  SEVERSON, Matthew ,  GHOSH, Kumar Kanti ,  JOSHI, Shishir

    IPC: G06F1/3296 ,  G06F1/20 ,  G06F1/28 ,  G06F1/3215 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/206 ,  G06F1/3243 ,  H04L12/10

    Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

    SYSTEMS AND METHODS FOR SLEEP CLOCK EDGE-BASED GLOBAL COUNTER SYNCHRONIZATION IN A CHIPLET SYSTEM
    2.
    发明申请
    SYSTEMS AND METHODS FOR SLEEP CLOCK EDGE-BASED GLOBAL COUNTER SYNCHRONIZATION IN A CHIPLET SYSTEM 审中-公开

    公开(公告)号：WO2023022810A1

    公开(公告)日：2023-02-23

    申请号：PCT/US2022/036642

    申请日：2022-07-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： NARALA, Naveen Kumar ,  SEVERSON, Matthew ,  ZHAO, Haobo

    IPC: G06F1/10

    Abstract: Various embodiments include methods and systems for providing sleep clock edge-based global counter synchronization in a multiple-chiplet system. A system-on-a-chip (SoC) may include a first chiplet including a first chiplet global counter subsystem, and a second chiplet including a second chiplet global counter subsystem. The SoC may further include an interface bus communicatively coupling the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to supply a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

    DIRECT CURRENT OFFSET CANCELLATION FOR MOBILE STATION MODEMS USING DIRECT CONVERSION
    4.
    发明申请
    DIRECT CURRENT OFFSET CANCELLATION FOR MOBILE STATION MODEMS USING DIRECT CONVERSION 审中-公开

    公开(公告)号：WO2003088606A3

    公开(公告)日：2003-10-23

    申请号：PCT/US2003/011070

    申请日：2003-04-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： HOLENSTEIN, Christian ,  KANG, Inyup ,  SEVERSON, Matthew

    IPC: H04L25/06

    Abstract: A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.

    DEVICE, EVENT AND MESSAGE PARAMETER ASSOCIATION IN A MULTI-DROP BUS
    8.
    发明申请
    DEVICE, EVENT AND MESSAGE PARAMETER ASSOCIATION IN A MULTI-DROP BUS 审中-公开

    公开(公告)号：WO2019036274A1

    公开(公告)日：2019-02-21

    申请号：PCT/US2018/045979

    申请日：2018-08-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： MISHRA, Lalan Jee ,  TILAK, Raghukul ,  ZHAO, Zhurang ,  ULMER, Elisha ,  WIETFELDT, Richard Dominic ,  SEVERSON, Matthew

    IPC: G06F13/42 ,  G06F13/38

    Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. A method performed at a device coupled to a serial bus includes determining that GPIO state information corresponding to a physical GPIO pin or signal is available in an event register that has a first bit width and includes information identifying one or more devices associated with the event register, and exchanging the GPIO state information with the one or more devices over the serial bus. The GPIO state information may be transmitted over the serial bus in accordance with configuration information stored in the event register. The configuration information may include an address identifying the one or more devices. The configuration information may include addressing information identifying a target register in the one or more devices. The configuration information may include information identifying a mode of communication for transmitting the GPIO state information.

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