公开(公告)号：EP3114544A1

公开(公告)日：2017-01-11

申请号：EP15711930.6

申请日：2015-02-28

Applicant: Qualcomm Incorporated

Inventor： IRANLI, Ali ,  KHAN, Moinul ,  LO, Haw-Jing

IPC: G06F1/32

CPC classification number: G06T1/60 ,  G06F1/3218 ,  G06F1/3265 ,  G06F1/3275 ,  G09G2330/022 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/153 ,  Y02D50/20

Abstract: Systems, methods, and computer programs are disclosed for reducing power consumption for static image display refresh in a dynamic random access memory (DRAM) memory system. One such method comprises: prefetching static image frame content from a DRAM memory device into a system cache; during a static display refresh operation, a display processor reads the static image frame content from the system cache while the DRAM memory device is in a power-saving, self-refresh state; and the display processor feeding the static image frame content to a mobile display.

Abstract translation: 系统，方法，和计算机程序盘游离缺失用于减少动态随机存取存储器（DRAM）的存储器系统，用于静态图像显示刷新功耗的一种搜索方法，包括：预取从DRAM存储器设备的静态图像帧内容到系统缓存;. 静态显示刷新操作期间，当DRAM器件处于省电，自刷新状态显示处理器将读取系统高速缓冲存储器中的静态图像帧内容; 和显示处理器供给的静态图像帧内容给移动显示。

公开(公告)号：EP3087452A1

公开(公告)日：2016-11-02

申请号：EP14825014.5

申请日：2014-12-12

Applicant: Qualcomm Incorporated

Inventor： CHUN, Dexter Tamio ,  LO, Haw-Jing ,  DROP, Michael

IPC: G06F1/32 ,  G11C7/10

CPC classification number: G06F12/06 ,  G06F1/3225 ,  G06F1/3275 ,  G06F13/1673 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

Abstract translation: 方面包括用于重新组织存储器中的数据存储器的计算设备，系统和方法，以激励小于用于读或写交易的存储器模块的所有存储器设备。 存储器件可以连接到单独的选择线，使得重新排序逻辑可以根据重新排序的存储器映射来确定存储器件激活事务。 重新排序逻辑可以重新排序存储器地址，使得由处理器为交易提供的存储器地址根据重新排序的存储器映射被转换为重新排序的存储器地址，而处理器不必改变其存储器地址方案。 重新排序的存储器映射可以提供由存储器件减少的能量消耗，或等待容忍过程的能量消耗和性能速度的平衡。

公开(公告)号：EP3061188A1

公开(公告)日：2016-08-31

申请号：EP14796621.2

申请日：2014-10-23

Applicant: Qualcomm Incorporated

Inventor： CHUN, Dexter ,  LO, Haw-Jing

IPC: H03M7/40 ,  H03M7/30

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  H03M7/40 ,  H03M7/6047

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data.

公开(公告)号：WO2018038805A1

公开(公告)日：2018-03-01

申请号：PCT/US2017/039636

申请日：2017-06-28

Applicant: QUALCOMM INCORPORATED

Inventor： SUH, Jungwon ,  CHUN, Dexter ,  LO, Haw-Jing

IPC: G06F13/16

Abstract: Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

Abstract translation: 系统和方法致力于减少处理器和存储器之间的数据传输的功耗。 检查要在处理器和存储器之间的数据总线上传送的数据的第一数据模式，并且如果存在第一数据模式，则在数据总线上抑制第一数据模式的传送。 而是，在第二总线上在处理器和存储器之间传送对应于第一数据模式的第一地址。 第一个地址小于第一个数据模式。 所述处理器包括处理器侧先进先出（FIFO），并且所述存储器包括存储器侧FIFO，其中所述第一数据模式存在于所述处理器侧FIFO中的所述第一地址处并且处于所述第一地址处 存储器端FIFO。

公开(公告)号：WO2017136099A2

公开(公告)日：2017-08-10

申请号：PCT/US2017/012514

申请日：2017-01-06

Applicant: QUALCOMM INCORPORATED

Inventor： ALAVOINE, Olivier ,  LEE, Sejoong ,  KAZI, Tauseef ,  BOOTH, Simon ,  REGINI, Edoardo ,  JAKUSHOKAS, Renatas ,  PATODIA, Saurabh ,  GEMAR, Jeffrey ,  LO, Haw-Jing ,  CHAMARTY, Vinod ,  ANDREEV, Boris ,  SHEN, Tao ,  BHASKARA, Aravind ,  WANG, Wenbiao ,  MOLLOY, Stephen

CPC classification number: G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Abstract translation: 各种方面包括用于管理计算设备上的存储器子系统的方法。 各种方面方法可以包括确定强制计算设备上的存储器子系统进入低功率模式的时间段，在确定的时间段期间禁止对存储器子系统的存储器访问请求，迫使存储器子系统进入低功率模式 所确定的时间周期，并且响应于所确定的时间段的期满，在所确定的时间段期间向存储器子系统执行存储器访问请求。

公开(公告)号：WO2017039950A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/045673

申请日：2016-08-05

Applicant: QUALCOMM INCORPORATED

Inventor： PARK, Hee Jun ,  LO, Haw-Jing ,  ROH, Keunsoo

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3275 ,  Y02D10/14

Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory power state transition timers. One embodiment of a method comprises receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device. An optimal value is determined for one or more memory power state transition timer settings. A current value is updated for the memory power state transition timer settings with the optimal value.

Abstract translation: 公开了用于动态调整存储器功率状态转换定时器的系统，方法和计算机程序。 方法的一个实施例包括接收影响与计算设备中的处理器耦合的存储器件的使用或性能的一个或多个参数。 确定一个或多个存储器功率状态转换定时器设置的最佳值。 对于具有最佳值的存储器电源状态转换定时器设置，更新当前值。

公开(公告)号：WO2015100038A1

公开(公告)日：2015-07-02

申请号：PCT/US2014/070123

申请日：2014-12-12

Applicant: QUALCOMM INCORPORATED

Inventor： CHUN, Dexter Tamio ,  LO, Haw-Jing ,  DROP, Michael

IPC: G06F1/32 ,  G11C7/10

CPC classification number: G06F12/06 ,  G06F1/3225 ,  G06F1/3275 ,  G06F13/1673 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

Abstract translation: 方面包括用于重新组织存储器中的数据存储器的计算设备，系统和方法，以激励小于用于读取或写入事务的存储器模块的所有存储器设备。 存储器件可以连接到单独的选择线，使得重新排序逻辑可以根据重新排序的存储器映射来确定存储器件激活事务。 重新排序逻辑可以重新排序存储器地址，使得由处理器为交易提供的存储器地址根据重新排序的存储器映射被转换为重新排序的存储器地址，而处理器不必改变其存储器地址方案。 重新排序的存储器映射可以提供由存储器件减少的能量消耗，或等待容忍过程的能量消耗和性能速度的平衡。

公开(公告)号：WO2015073613A1

公开(公告)日：2015-05-21

申请号：PCT/US2014/065356

申请日：2014-11-13

Applicant: QUALCOMM INCORPORATED

Inventor： LO, Haw-Jing ,  CHUN, Dexter

IPC: G11C7/10 ,  G06F13/16

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3253 ,  G06F7/764 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4096

Abstract: Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.

Abstract translation: 公开了用于降低存储器I / O功率的系统和方法。 一个实施例是包括片上系统（SoC），DRAM存储器件和数据屏蔽功率降低模块的系统。 SoC包括一个内存控制器。 DRAM存储器件通过多个DQ引脚耦合到存储器控制器。 数据屏蔽功率降低模块包括被配置为在数据屏蔽操作期间将DQ引脚驱动到功率节省状态的逻辑。

公开(公告)号：WO2015061541A1

公开(公告)日：2015-04-30

申请号：PCT/US2014/061921

申请日：2014-10-23

Applicant: QUALCOMM INCORPORATED

Inventor： CHUN, Dexter ,  LO, Haw-Jing

IPC: H03M7/40 ,  H03M7/30

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  H03M7/40 ,  H03M7/6047

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data.

Abstract translation: 公开了用于节省存储器系统中的功耗的系统和方法。 一种这样的系统包括片上系统（SoC）和编码器。 SoC包括用于访问耦合到SoC的动态随机存取存储器（DRAM）存储器系统的一个或多个存储器客户端。 编码器驻留在SoC上，并被配置为通过根据压缩方案对所接收的存储器数据进行编码并将编码的存储器数据提供给DRAM存储器系统来减少从存储器客户机接收的存储器数据的数据活动因子。 DRAM存储器系统被配置为根据压缩方案将经编码的存储器数据解码为接收的存储器数据。

公开(公告)号：EP3411775B1

公开(公告)日：2019-12-25

申请号：EP17701232.5

申请日：2017-01-06

Applicant: Qualcomm Incorporated

Inventor： ALAVOINE, Olivier ,  LEE, Sejoong ,  KAZI, Tauseef ,  BOOTH, Simon ,  REGINI, Edoardo ,  JAKUSHOKAS, Renatas ,  PATODIA, Saurabh ,  GEMAR, Jeffrey ,  LO, Haw-Jing ,  CHAMARTY, Vinod ,  ANDREEV, Boris ,  SHEN, Tao ,  BHASKARA, Aravind ,  WANG, Wenbiao ,  MOLLOY, Stephen

IPC: G06F1/32