Abstract:
This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.
Abstract:
Certain aspects of the present disclosure generally relate to methods and apparatus for generating oscillating signals. For example, certain aspects of the present disclosure provide a phase-locked loop (PLL) having a first switch coupled to a sampling input node of the PLL, an integrator coupled to an output of the sampling circuit, and a voltage-controlled oscillator (VCO) having an input coupled to an output of the integrator. In certain aspects, the PLL may also include a feedback path coupled to an output of the VCO and a control input of the first switch.
Abstract:
Certain aspects of the present disclosure provide methods and apparatus for dynamically adjusting a voltage-controlled oscillator (VCO) frequency, a local oscillator (LO) divider ratio, and/or a receive path when adding or discontinuing reception of a component carrier (CC) in a carrier aggregation (CA) scheme. This dynamic adjustment is utilized to avoid (or at least reduce) VCO, LO, and transmit signal coupling issues with multiple component carriers, with minimal (or at least reduced) current consumption by the VCO and the LO divider.
Abstract:
Locking multiple VCOs to generate a plurality of LO frequencies, including: receiving a plurality of divided VCO feedback signals from a plurality of VCOs; receiving a reference signal multiplied by a predetermined number of the plurality of VCOs; generating and processing the predetermined number of phase differences between the multiplied reference signal and the plurality of divided VCO feedback signals in a single PLL circuit including a digital loop filter to receive and process the phase differences and generate (produce) a filter output, wherein the digital loop filter includes a plurality of delay cells equal to the predetermined number; and generating and outputting (delayed) control voltages for the plurality of VCOs based on the filter output.
Abstract:
An apparatus for generating an oscillating output signal includes an inductive-capacitive (LC) circuit and a current tuning circuit. The LC circuit includes a primary inductor and a varactor coupled to the primary inductor. A capacitance of the varactor is responsive to a voltage at a control input of the varactor. The current tuning circuit includes a secondary inductor and a current driving circuit coupled to the secondary inductor. The current driving circuit is responsive to a current at a control input of the current driving circuit. An effective inductance of the primary inductor is adjustable via magnetic coupling to the secondary inductor, and a frequency of the oscillating output signal is responsive to the effective inductance of the primary inductor and to the capacitance of the varactor.
Abstract:
In certain aspects, a sampler includes a sampling capacitor, a precharge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference-voltage circuit coupled to the sampling capacitor. The reference-voltage circuit is configured to generate a reference voltage based on a supply voltage, and generate a voltage difference between a voltage on the sampling capacitor and the reference voltage.
Abstract:
A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.
Abstract:
Certain aspects of the present disclosure provide techniques and apparatus for glitch-free bandwidth switching in a phase-locked loop (PLL). One example PLL generally includes a voltage-controlled oscillator (VCO) comprising a first variable capacitive element and a second variable capacitive element and a bandwidth adjustment circuit comprising a first switch in parallel with a resistor of a resistor-capacitor (RC) network. The bandwidth adjustment circuit is configured to open the first switch for a first bandwidth mode, close the first switch in a transition from the first bandwidth mode to a second bandwidth mode, and control a capacitance of the second variable capacitive element based on a voltage of a node of the RC network.
Abstract:
Reconfiguring a transceiver design using a plurality of frequency synthesizers and a plurality of carrier aggregation (CA) receiver (Rx) and transmitter (Tx) chains, the method including: connecting a first frequency synthesizer to a first CA Tx chain; connecting the plurality of frequency synthesizers to the plurality of CA Rx chains, wherein a second frequency synthesizer of the plurality of frequency synthesizers is connected as a shared synthesizer to a first CA Rx chain and a second CA Tx chain.
Abstract:
Certain aspects of the present disclosure provide multi-way diversity receivers with multiple synthesizers. Such a multi-way diversity receiver may be implemented in a carrier aggregation (CA) transceiver. One example wireless reception diversity circuit generally includes three or more receive paths for processing received signals and two or more frequency synthesizing circuits configured to generate local oscillating signals to downconvert the received signals. Each of the frequency synthesizing circuits is shared by at most two of the receive paths, and each pair of the frequency synthesizing circuits may generate a pair of local oscillating signals having the same frequency.