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    MULTIMODE FREQUENCY MULTIPLIER
    11.
    发明申请
    MULTIMODE FREQUENCY MULTIPLIER 审中-公开

    公开(公告)号：WO2022226462A2

    公开(公告)日：2022-10-27

    申请号：PCT/US2022/071417

    申请日：2022-03-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZHANG, Yan ,  ZHU, Yunliang ,  TANG, Yiwu

    IPC: H03B19/14 ,  H03K3/03 ,  H03B19/10 ,  H03B5/1221 ,  H03D7/14 ,  H03K3/0315 ,  H03K5/00006 ,  H04B1/0483 ,  H04L27/362

    Abstract: This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

    SAMPLING PHASE-LOCKED LOOP (PLL)
    12.
    发明申请
    SAMPLING PHASE-LOCKED LOOP (PLL) 审中-公开

    公开(公告)号：WO2018140263A1

    公开(公告)日：2018-08-02

    申请号：PCT/US2018/013937

    申请日：2018-01-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： PARK, Dongmin ,  PARK, Jong Min ,  TANG, Yiwu

    IPC: H03L7/091 ,  H03L7/085

    CPC classification number: H03L7/091 ,  H03L7/085 ,  H03L7/099 ,  H04L7/0331

    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating oscillating signals. For example, certain aspects of the present disclosure provide a phase-locked loop (PLL) having a first switch coupled to a sampling input node of the PLL, an integrator coupled to an output of the sampling circuit, and a voltage-controlled oscillator (VCO) having an input coupled to an output of the integrator. In certain aspects, the PLL may also include a feedback path coupled to an output of the VCO and a control input of the first switch.

    LOCKING MULTIPLE VOLTAGE-CONTROLLED OSCILLATORS WITH A SINGLE PHASE-LOCKED LOOP
    14.
    发明申请
    LOCKING MULTIPLE VOLTAGE-CONTROLLED OSCILLATORS WITH A SINGLE PHASE-LOCKED LOOP 审中-公开
    带有单相锁定环路的锁定多电压控制振荡器

    公开(公告)号：WO2015156969A1

    公开(公告)日：2015-10-15

    申请号：PCT/US2015/020934

    申请日：2015-03-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： TANG, Yiwu ,  PARK, Jong Min ,  SAYILIR, Serkan ,  NARATHONG, Chiewcharn

    IPC: H03L7/087 ,  H03L7/093

    CPC classification number: H03L7/099 ,  H03L7/081 ,  H03L7/093

    Abstract: Locking multiple VCOs to generate a plurality of LO frequencies, including: receiving a plurality of divided VCO feedback signals from a plurality of VCOs; receiving a reference signal multiplied by a predetermined number of the plurality of VCOs; generating and processing the predetermined number of phase differences between the multiplied reference signal and the plurality of divided VCO feedback signals in a single PLL circuit including a digital loop filter to receive and process the phase differences and generate (produce) a filter output, wherein the digital loop filter includes a plurality of delay cells equal to the predetermined number; and generating and outputting (delayed) control voltages for the plurality of VCOs based on the filter output.

    Abstract translation: 锁定多个VCO以产生多个LO频率，包括：从多个VCO接收多个分割的VCO反馈信号; 接收乘以所述多个VCO的预定数量的参考信号; 在包括数字环路滤波器的单个PLL电路中产生和处理倍增参考信号与多个分压VCO反馈信号之间的预定数量的相位差，以接收和处理相位差并产生（产生）滤波器输出，其中， 数字环路滤波器包括等于预定数量的多个延迟单元; 以及基于滤波器输出产生并输出（延迟的）多个VCO的控制电压。

    APPARATUS AND METHOD FOR GENERATING AN OSCILLATING OUTPUT SIGNAL
    15.
    发明申请
    APPARATUS AND METHOD FOR GENERATING AN OSCILLATING OUTPUT SIGNAL 审中-公开
    用于产生振荡输出信号的装置和方法

    公开(公告)号：WO2014120602A1

    公开(公告)日：2014-08-07

    申请号：PCT/US2014/013173

    申请日：2014-01-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： TANG, Yiwu ,  HU, Jianyun ,  NARATHONG, Chiewcharn

    IPC: H03C3/09

    CPC classification number: H03L7/16 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1256 ,  H03B5/1296 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0958 ,  H03L7/00 ,  H03L7/07 ,  H03L7/101 ,  H03L7/104 ,  H03L7/187

    Abstract: An apparatus for generating an oscillating output signal includes an inductive-capacitive (LC) circuit and a current tuning circuit. The LC circuit includes a primary inductor and a varactor coupled to the primary inductor. A capacitance of the varactor is responsive to a voltage at a control input of the varactor. The current tuning circuit includes a secondary inductor and a current driving circuit coupled to the secondary inductor. The current driving circuit is responsive to a current at a control input of the current driving circuit. An effective inductance of the primary inductor is adjustable via magnetic coupling to the secondary inductor, and a frequency of the oscillating output signal is responsive to the effective inductance of the primary inductor and to the capacitance of the varactor.

    Abstract translation: 用于产生振荡输出信号的装置包括电感 - 电容（LC）电路和电流调谐电路。 LC电路包括耦合到初级电感器的初级电感器和变容二极管。 变容二极管的电容响应于变容二极管的控制输入端的电压。 当前调谐电路包括二次电感器和耦合到次级电感器的电流驱动电路。 电流驱动电路响应于电流驱动电路的控制输入处的电流。 初级电感器的有效电感可通过与次级电感器的磁耦合进行调节，振荡输出信号的频率响应于初级电感器的有效电感和变容二极管的电容。

    GLITCH-FREE BANDWIDTH-SWITCHING SCHEME FOR AN ANALOG PHASE-LOCKED LOOP (PLL)
    18.
    发明申请
    GLITCH-FREE BANDWIDTH-SWITCHING SCHEME FOR AN ANALOG PHASE-LOCKED LOOP (PLL) 审中-公开
    用于模拟锁相环（PLL）的无刷宽带切换方案

    公开(公告)号：WO2017052899A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/048214

    申请日：2016-08-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZHUANG, Jingcheng ,  PARK, Jong Min ,  LEUNG, Lai Kan ,  TANG, Yiwu

    IPC: H03L7/107

    CPC classification number: H03L7/093 ,  H03L7/099 ,  H03L7/1072 ,  H03L7/1075

    Abstract: Certain aspects of the present disclosure provide techniques and apparatus for glitch-free bandwidth switching in a phase-locked loop (PLL). One example PLL generally includes a voltage-controlled oscillator (VCO) comprising a first variable capacitive element and a second variable capacitive element and a bandwidth adjustment circuit comprising a first switch in parallel with a resistor of a resistor-capacitor (RC) network. The bandwidth adjustment circuit is configured to open the first switch for a first bandwidth mode, close the first switch in a transition from the first bandwidth mode to a second bandwidth mode, and control a capacitance of the second variable capacitive element based on a voltage of a node of the RC network.

    Abstract translation: 本公开的某些方面提供了在锁相环（PLL）中无毛刺带宽切换的技术和装置。 一个示例PLL通常包括包括第一可变电容元件和第二可变电容元件的压控振荡器（VCO），以及包括与电阻器 - 电容器（RC）网络的电阻器并联的第一开关的带宽调整电路。 带宽调整电路被配置为在第一带宽模式下打开第一开关，在从第一带宽模式到第二带宽模式的转变中关闭第一开关，并且基于第一可变电容元件的电压来控制第二可变电容元件的电容 RC网络的一个节点。

    MULTI-WAY DIVERSITY RECEIVER WITH MULTIPLE SYNTHESIZERS IN A CARRIER AGGREGATION TRANSCEIVER
    20.
    发明申请
    MULTI-WAY DIVERSITY RECEIVER WITH MULTIPLE SYNTHESIZERS IN A CARRIER AGGREGATION TRANSCEIVER 审中-公开
    多方位接收器与多个合成器在载波聚合收发器

    公开(公告)号：WO2015175109A1

    公开(公告)日：2015-11-19

    申请号：PCT/US2015/024189

    申请日：2015-04-03

    Applicant: QUALCOMM INCORPORATED

    Inventor： LEUNG, Lai Kan ,  NARATHONG, Chiewcharn ,  RANGARAJAN, Rajagopalan ,  PAN, Dongling ,  TANG, Yiwu ,  TASIC, Aleksandar Miodrag

    IPC: H04B1/00

    CPC classification number: H04B7/0897 ,  H04B1/0082 ,  H04B1/16 ,  H04L27/152

    Abstract: Certain aspects of the present disclosure provide multi-way diversity receivers with multiple synthesizers. Such a multi-way diversity receiver may be implemented in a carrier aggregation (CA) transceiver. One example wireless reception diversity circuit generally includes three or more receive paths for processing received signals and two or more frequency synthesizing circuits configured to generate local oscillating signals to downconvert the received signals. Each of the frequency synthesizing circuits is shared by at most two of the receive paths, and each pair of the frequency synthesizing circuits may generate a pair of local oscillating signals having the same frequency.

    Abstract translation: 本公开的某些方面提供具有多个合成器的多路分集接收机。 这种多路分集接收机可以在载波聚合（CA）收发机中实现。 一个示例性的无线接收分集电路通常包括用于处理接收信号的三个或更多个接收路径和被配置为产生本地振荡信号以下变频接收信号的两个或多个频率合成电路。 每个频率合成电路由至多两个接收路径共享，并且每对频率合成电路可以产生具有相同频率的一对本地振荡信号。

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