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公开(公告)号：FR2586517B1
公开(公告)日：1991-11-22
申请号：FR8611964
申请日：1986-08-21
Applicant: RCA CORP
Inventor： BESSLER ROGER FRANK , ARBEITER JAMES HENRY , SINNIGER JOSEPH OWEN
IPC: H04N5/21 , G06F15/00 , G06F17/10 , G06K9/54 , G06T1/00 , G08C13/00 , H03H17/00 , H03H17/02 , H04N7/26 , H04N7/54 , H03M7/30 , G01R23/167 , H04N5/14
Abstract: The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.
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公开(公告)号：GB2143046B
公开(公告)日：1986-12-10
申请号：GB8415811
申请日：1984-06-21
Applicant: RCA CORP
Inventor： CARLSON CURTIS RAYMOND , ARBEITER JAMES HENRY , BESSLER ROGER FRANK , ADELSON EDWARD HOWARD , ANDERSON CHARLES HAMMOND , LIMBERG ALLEN LEROY
IPC: G01R23/167 , G06F17/10 , H04N7/26 , G01R23/165
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公开(公告)号：FR2560700A1
公开(公告)日：1985-09-06
申请号：FR8502983
申请日：1985-02-28
Applicant: RCA CORP
Inventor： CARLSON CURTIS RAYMOND , ARBEITER JAMES HENRY , BESSLER ROGER FRANK , ADELSON EDWARD HOWARD , ANDERSON CHARLES HAMMOND , LIMBERG ALLEN LEROY
IPC: H04N5/14 , G01R23/165 , G01R23/167 , G06F3/05 , G06F17/10 , G06T11/60 , H03H17/02 , H03M7/30 , H04N7/26 , G06F15/62 , H04N5/91 , H04N9/64
Abstract: PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.
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公开(公告)号：GB2179818B
公开(公告)日：1989-08-09
申请号：GB8620142
申请日：1986-08-19
Applicant: RCA CORP
Inventor： BESSLER ROGER FRANK , ARBEITER JAMES HENRY , SINNIGER JOSEPH OWEN
IPC: H04N5/21 , G06F15/00 , G06F17/10 , G06K9/54 , G06T1/00 , G08C13/00 , H03H17/00 , H03H17/02 , H04N7/26 , H04N7/54
Abstract: The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.
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公开(公告)号：DE3628349A1
公开(公告)日：1987-03-05
申请号：DE3628349
申请日：1986-08-21
Applicant: RCA CORP
Inventor： BESSLER ROGER FRANK , ARBEITER JAMES HENRY , SINNIGER JOSEPH OWEN
IPC: H04N5/21 , G06F15/00 , G06F17/10 , G06K9/54 , G06T1/00 , G08C13/00 , H03H17/00 , H03H17/02 , H04N7/26 , H04N7/54 , G06F15/62 , G06F7/00
Abstract: The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.
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Patent Agency Ranking
公开(公告)号：FR2586517A1
公开(公告)日：1987-02-27
申请号：FR8611964
申请日：1986-08-21
Applicant: RCA CORP
Inventor： BESSLER ROGER FRANK , ARBEITER JAMES HENRY , SINNIGER JOSEPH OWEN
IPC: H04N5/21 , G06F15/00 , G06F17/10 , G06K9/54 , G06T1/00 , G08C13/00 , H03H17/00 , H03H17/02 , H04N7/26 , H04N7/54 , H03M7/30 , G01R23/167 , H04N5/14
Abstract: The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.
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公开(公告)号：BR8403141A
公开(公告)日：1985-06-11
申请号：BR8403141
申请日：1984-06-27
Applicant: RCA CORP
Inventor： CARLSON CURTIS RAYMOND , ARBEITER JAMES HENRY , BESSLER ROGER FRANK , ADELSON EDWARD HOWARD , ANDERSON CHARLES HAMMOND , LIMBERG ALLEN LEROY
IPC: H04N5/14 , G01R23/165 , G01R23/167 , G06F3/05 , G06F17/10 , G06T11/60 , H03H17/02 , H03M7/30 , H04N7/26 , H04N17/00
Abstract: PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.
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公开(公告)号：GB2143046A
公开(公告)日：1985-01-30
申请号：GB8415811
申请日：1984-06-21
Applicant: RCA CORP
Inventor： CARLSON CURTIS RAYMOND , ARBEITER JAMES HENRY , BESSLER ROGER FRANK , ADELSON EDWARD HOWARD , ANDERSON CHARLES HAMMOND , LIMBERG ALLEN LEROY
IPC: G01R23/167 , G06F17/10 , H04N7/26 , G01R23/165
Abstract: Apparatus for performing spectral analysis comprises a cascade connection of low-pass sampling filters 100-1 to 100-N operated at successively lower sampling rates. Thus an input signal Go, which may be a video or an audio signal, is transformed into Loplacian component signals Lo to LN-1, and a remnant Gaussian output GN. The apparatus may be embodied in digital form wherein each of the filters comprises a digital convolution filter. In the alternative, analogue embodiments may employ charge coupled devices as convolution or interpolation filters. Apparatus is also disclosed for synthesising a signal by recombining the spectrum analysis components.
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公开(公告)号：DK311084A
公开(公告)日：1984-12-28
申请号：DK311084
申请日：1984-06-26
Applicant: RCA CORP
Inventor： CARLSON CURTIS RAYMOND , ARBEITER JAMES HENRY , BESSLER ROGER FRANK
IPC: H04N5/14 , G01R23/165 , G01R23/167 , G06F3/05 , G06F17/10 , G06T11/60 , H03H17/02 , H03M7/30 , H04N7/26 , G01R , H04N
Abstract: PURPOSE: To efficiently and accurately obtain a complex signal by inserting a delay and forming information samples, simultaneously generated in each adder when signals, having time deviation in a signal group is transmitted thereby composing the composite signal in real time. CONSTITUTION: 1st input terminals of relay means 100-2 to 100-n are connected to the 1st output terminals of relay means 100-1 to (n-1) respectively. Then, sampling frequency clocks CL1 to CLn are applied to other input terminals, and other input terminals are corrected by correcting parts 345 to 349, via delays 340 to 344 and connected to adders ADD 359 to 363, respectively. For example, when a thirdly generated signal and a fourthly generated signal are combined and transmitted, it causes time deviation. Then, the 3rd signal precedented generated is delayed for a prescribed time by the delay 342 to form an information sample practically simultaneously generated in the adder 359. Thus, since the composite signal is composed only by a realtime processing, a complex signal is obtained. efficiently and accurately.
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公开(公告)号：ZA844037B
公开(公告)日：1984-12-24
申请号：ZA844037
申请日：1984-05-28
Applicant: RCA CORP
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