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公开(公告)号：FI79228B
公开(公告)日：1989-07-31
申请号：FI854165
申请日：1985-10-24
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY
Abstract: A television receiver includes a character generator for producing alphanumeric data or graphic symbols to be displayed along with a received video signal. An oscillator, locked to a multiple of the color subcarrier frequency of the video signal, supplies a clock signal to the character generator for controlling the timing of displayed character elements. A delay circuit coupled to the character generator and controlled by a measuring circuit imparts an effective delay to the character elements in proportion to the time difference between a transition of the clock signal and the horizontal synchronizing component of the video signal. The delay compensates for temporal and spacial distortions of displayed characters which otherwise would tend to occur when the ratio of the color subcarrier frequency with respect to the horizontal line rate of the video signal is "non-standard" (e.g., other than 910:1 for NTSC or 1135:1 for PAL).
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公开(公告)号：AU579860B2
公开(公告)日：1988-12-15
申请号：AU4165985
申请日：1985-04-24
Applicant: RCA CORP
Inventor： STOUGHTON JOHN WILLIAM , WILLIS DONALD HENRY
Abstract: A beam current limiting (BCL) control apparatus for a digital television system includes a control unit (31) for reducing excessive beam currents, by controlling an analog-to-digital control means (3a) for the analog-to-digital converter (ADC) (3), which converts an analog composite video signal, including both luminance and chrominance components, to corresponding digital samples. The analog-to-digital control means (3a) can fulfil its function by controlling the reference voltage for the ADC (3). A switching circuit (33) may be included for preventing the reference voltage from being changed in response to the beam current during horizontal blanking intervals so as to inhibit interference with digital synchronization component detection and automatic chrominance control. A clamping circuit (35) is coupled to the ADC (3) to inhibit the conversion of portions of the composite video signal extending from the black level (0 IRE umts) to the sync tips from being affected by the BCL operation. This inhibits the BCL operation from adversely affecting the reproduction of details in dark portions of an image.
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公开(公告)号：FR2563068B1
公开(公告)日：1988-11-10
申请号：FR8505473
申请日：1985-04-11
Applicant: RCA CORP
Inventor： FLING RUSSEL THOMAS , WILLIS DONALD HENRY , MCNEELY DAVID LOWELL
Abstract: A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.
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公开(公告)号：IT1193320B
公开(公告)日：1988-06-15
申请号：IT2547979
申请日：1979-09-04
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY , HICKS JAMES EDWARD
Abstract: A controllable switch 14 is coupled to a source 10 of unregulated direct voltage and in a closed loop with a filter inductor 16 and a storage capacitor 18 and has its on-off state controlled at the horizontal deflection rate, e.g. by deflection circuit 22, to control the voltage across the capacitor. A diode 24 is coupled with the filter inductor and storage capacitor to form a second series circuit through which current can continue to (ow in the inductor 16 when the controllable switch is opened. The controllable switch is used to regulate the voltage applied to the horizontal deflection circuit 22. A turn-off winding couples a retrace pulse to the switch 14 during each horizontal retrace interval in preparation for the following regulation interval. The current variations in the filter inductor cause the diode to become nonconductive at times, thereby changing the average time during which the filter inductor parallels the deflection winding and varying the retrace pulse duration in such a manner as to improve the regulation.
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公开(公告)号：DE3737627A1
公开(公告)日：1988-05-11
申请号：DE3737627
申请日：1987-11-05
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY
Abstract: An interpolating apparatus for generating a pair of non-identical, interlaced fields from a single stored field of video signal. One of the interlaced fields is generated by adding three-fourths of one line's amplitude to one-fourth of the next line's amplitude. The other interlaced field is generated by adding one-fourth of said one line's amplitude to three-fourths of the next line's amplitude.
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Patent Agency Ranking
公开(公告)号：IT1183466B
公开(公告)日：1987-10-22
申请号：IT1975285
申请日：1985-03-05
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY
Abstract: In a digital video signal processing system including an image reproducing kinescope and a digital-to-analog converter (DAC), excessive kinescope beam current are automatically limited in response to a control signal which varies a reference voltage for the DAC such that the peak-to-peak amplitude of analog video signals from the DAC is reduced. A version of the control signal is applied to the output of the DAC with a magnitude and polarity for substantially negating unwanted shifts of the video signal black level during the beam current limiting mode.
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公开(公告)号：GB2157530B
公开(公告)日：1987-07-15
申请号：GB8509266
申请日：1985-04-11
Applicant: RCA CORP
Inventor： FLING RUSSELL THOMAS , WILLIS DONALD HENRY , MCNEELY DAVID LOWELL
Abstract: A signal overload circuit for use in e.g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.
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公开(公告)号：IT1174086B
公开(公告)日：1987-07-01
申请号：IT2087384
申请日：1984-05-10
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY
Abstract: A color television receiver includes a network for automatically limiting excessive kinescope beam currents developed in response to video signal image information, and a white balance control network for automatically controlling the white level drive (gain) characteristics of the kinescope in response to a white drive reference signal applied to the video signal path during given measuring intervals. A control signal developed by the beam current limiter network, otherwise applied to the video signal path, is decoupled from the video signal path during the white level measuring intervals to prevent distortion of the white level control function.
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公开(公告)号：FI863479A
公开(公告)日：1987-03-04
申请号：FI863479
申请日：1986-08-27
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J , WILLIS DONALD HENRY , FLING RUSSELL THOMAS
Abstract: System performance of picture-in-picture video display systems is dependent on critical timing relationships between the incoming signals and the clock signals used to sample and display both the large picture and small picture signals. Video signals from various sources, e.g. VTR's, tend to have jittering time bases which may cause the small image to appear jagged or tilted. This distortion in the small image may be reduced by effecting adaptive signal delays in the small picture signal responsive to the relative phase of the system clock signal with respect to the horizontal synchronizing pulses of the large and/or small picture signal. One phase measure is used to control an interpolator which combines successive samples of the small picture signal in proportions to develop sample values corresponding to samples that would have occurred had the small picture signal been sampled by a clock properly aligned to the small picture horizontal synchronizing pulses. A second phase measure is used to delay the clock signal used to display the small picture so that the clock pulses that define the edges of the small picture occurs with the same timing relative to the large picture horizontal synchronizing pulses form line-to-line.
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公开(公告)号：FR2585916A1
公开(公告)日：1987-02-06
申请号：FR8611063
申请日：1986-07-30
Applicant: RCA CORP
Inventor： WILLIS DONALD HENRY , FLING RUSSEL THOMAS , CHRISTOPHER TODD J
Abstract: A speed-up memory doubles the field rate of a video input signal by repeating each field to reduce flicker when the double field rate signal is displayed. Read/write clocks for controlling the memory are locked to the color subcarrier of the video input signal thereby tending to produce visual artifacts in the displayed image due to clock skew relative to sync when non-standard video signals are processed. The skew errors are corrected by circuitry which measures the skew of the read and write clocks and delays the video signal as a function of a difference between the clock skew measurements.
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