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    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME
    11.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220375941A1

    公开(公告)日：2022-11-24

    申请号：US17574666

    申请日：2022-01-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KISEOK LEE ,  HUI-JUNG KIM ,  MIN HEE CHO

    IPC: H01L27/108 ,  H01L29/786

    Abstract: A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

    SEMICONDUCTOR MEMORY DEVICE
    13.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240349492A1

    公开(公告)日：2024-10-17

    申请号：US18543279

    申请日：2023-12-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MYEONG-DONG LEE ,  SEUNG-BO KO ,  KEUNNAM KIM ,  JONGMIN KIM ,  HUI-JUNG KIM ,  TAEJIN PARK ,  DONGHYUK AHN ,  KISEOK LEE ,  MINYOUNG LEE ,  INHO CHA

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34

    Abstract: A semiconductor memory device include first and second active patterns extending in a first direction and spaced apart from each other in a second direction crossing the first direction. The first and second active patterns include a first and second edge portions spaced apart from each other in the first direction, and a center portion therebetween. Bit line node contacts are on the center portions. Bit lines are on the bit line node contacts and extend in a third direction crossing the first and second directions. The center portions of the first and second active patterns are sequentially disposed in the second direction. Each of the bit line node contacts has a first width at a level of a top surface, a second width at a level of a bottom surface, and a third width between the top and bottom surfaces less than the first and second widths.

    SEMICONDUCTOR DEVICES
    14.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240324186A1

    公开(公告)日：2024-09-26

    申请号：US18405026

    申请日：2024-01-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KISEOK LEE ,  Chansic YOON

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

    Abstract: A semiconductor device includes active patterns on a substrate, gate structures in recesses of the active patterns and extending in the first direction, first contact plugs electrically connected to opposite edge portions of each of the active patterns, respectively, the first contact plugs being spaced apart from each other in each of the first and second directions and aligned in each of the first and second directions, first insulation spacers surrounding sidewalls of the first contact plugs, the first insulation spacers filling spaces between the first contact plugs in the second direction, a bit line structure filling an opening extending in the second direction between the first insulation spacers, the bit line structure contacting central portions of the active patterns, and a capacitor electrically connected to each of the first contact plugs.

    SEMICONDUCTOR MEMORY DEVICE
    15.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230309289A1

    公开(公告)日：2023-09-28

    申请号：US18094719

    申请日：2023-01-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyungeun CHOI ,  KISEOK LEE ,  HAEJOON LEE ,  SEUNGJAE JUNG

    IPC: H10B80/00 ,  H10B12/00

    CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05 ,  H10B12/50 ,  H10B80/00

    Abstract: A semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, the stack having a staircase structure on the second region. The word lines may extend from the first region to the second region in the first direction. Each of the word lines may include sub-gate electrodes, which extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region.

    CAPACITOR STRUCTURE
    17.
    发明申请
    CAPACITOR STRUCTURE 有权

    公开(公告)号：US20250048617A1

    公开(公告)日：2025-02-06

    申请号：US18736153

    申请日：2024-06-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： BYEUNGMOO KANG ,  SEOKHAN PARK ,  KISEOK LEE

    IPC: H10B12/00

    Abstract: A capacitor structure may include a plurality of lower electrodes arranged in a first direction and a second direction perpendicular to the first direction, a supporter including a plurality of openings and adjoining the plurality of lower electrodes, a dielectric layer covering the supporter and the plurality of lower electrodes, and an upper electrode covering the dielectric layer, where each of the plurality of openings contacts four lower electrodes, and where the plurality of openings contact opposite sides of the plurality of lower electrodes along the first direction and the second direction.

    SEMICONDUCTOR MEMORY DEVICE
    19.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220246180A1

    公开(公告)日：2022-08-04

    申请号：US17481583

    申请日：2021-09-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： WONSOK LEE ,  MIN TAE RYU ,  WOO BIN SONG ,  KISEOK LEE ,  MINSU LEE ,  MIN HEE CHO

    IPC: G11C5/06 ,  H01L29/06 ,  H01L27/108

    Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    20.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210296237A1

    公开(公告)日：2021-09-23

    申请号：US17097337

    申请日：2020-11-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HYO-SUB KIM ,  SOHYUN PARK ,  DAEWON KIM ,  DONGOH KIM ,  EUN A KIM ,  CHULKWON PARK ,  TAEJIN PARK ,  KISEOK LEE ,  SUNGHEE HAN

    IPC: H01L23/535 ,  H01L27/108 ,  H01L23/532 ,  H01L21/768

    Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

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