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    Semiconductor Memory Devices
    1.
    发明专利
    Semiconductor Memory Devices 未知

    公开(公告)号：SG10201900899UA

    公开(公告)日：2019-09-27

    申请号：SG10201900899U

    申请日：2019-01-31

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： KISEOK LEE ,  BONG-SOO KIM ,  JIYOUNG KIM ,  HUI-JUNG KIM ,  SEOKHAN PARK ,  HUNKOOK LEE ,  YOOSANG HWANG

    IPC: H01L27/108 ,  H01L23/528

    Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes. FIG. 5

    Three-Dimensional Semiconductor Memory Device
    2.
    发明专利
    Three-Dimensional Semiconductor Memory Device 未知

    公开(公告)号：SG10202007886XA

    公开(公告)日：2021-05-28

    申请号：SG10202007886X

    申请日：2020-08-18

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： JOONGCHAN SHIN ,  CHANGKYU KIM ,  HUI-JUNG KIM ,  ILJAE SHIN ,  TAEHYUN AN ,  KISEOK LEE ,  EUNJU CHO ,  HYUNGEUN CHOI ,  SUNG-MIN PARK ,  AHRAM LEE ,  SANGYEON HAN ,  YOOSANG HWANG

    Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

    SEMICONDUCTOR MEMORY DEVICES
    3.
    发明专利
    SEMICONDUCTOR MEMORY DEVICES 未知

    公开(公告)号：SG10201911466SA

    公开(公告)日：2020-01-30

    申请号：SG10201911466S

    申请日：2018-07-17

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： JIYOUNG KIM ,  KISEOK LEE ,  BONG-SOO KIM ,  JUNSOO KIM ,  DONGSOO WOO ,  KYUPIL LEE ,  HYEONGSUN HONG ,  YOOSANG HWANG

    Abstract: The present invention relates to a semiconductor memory device. More specifically, the semiconductor memory device comprises: a plurality of memory cell transistors vertically stacked on a substrate; a first conductive line connected to a source of at least one of the memory cell transistors; a second conductive line connected to gates of the memory cell transistors; and a capacitor connected to a drain of at least one of the memory cell transistors. The capacitor includes a first electrode horizontally extended in a first direction parallel to the upper surface of the substrate from the drain. One of the first and second conductive lines horizontally extends in a second direction intersecting the first direction, and the other one of the first and second conductive lines vertically extends in a third direction perpendicular to the upper surface of the substrate.

    SEMICONDUCTOR MEMORY DEVICES
    4.
    发明专利
    SEMICONDUCTOR MEMORY DEVICES 未知

    公开(公告)号：SG10201806114YA

    公开(公告)日：2019-04-29

    申请号：SG10201806114Y

    申请日：2018-07-17

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： JIYOUNG KIM ,  KISEOK LEE ,  BONG-SOO KIM ,  JUNSOO KIM ,  DONGSOO WOO ,  KYUPIL LEE ,  HYEONGSUN HONG ,  YOOSANG HWANG

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors. FIG. 26

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210057419A1

    公开(公告)日：2021-02-25

    申请号：US16833919

    申请日：2020-03-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： DONGSUK SHIN ,  JIYOUNG KIM ,  HOKYUN AN ,  CHAN MIN LEE ,  EUNJU CHO ,  HUI-JUNG KIM ,  JOONGCHAN SHIN ,  TAEHYUN AN ,  HYUNGEUN CHOI ,  YOOSANG HWANG ,  KISEOK LEE

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250016979A1

    公开(公告)日：2025-01-09

    申请号：US18616352

    申请日：2024-03-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JONGMIN KIM ,  CHANSIC YOON ,  KISEOK LEE

    IPC: H10B12/00

    Abstract: A semiconductor device may include first and second active patterns, first and second gate structures, a source/drain layer, a bit line structure, a contact plug structure, and a capacitor. The first and second active patterns are on a cell region and a peripheral circuit region of a substrate, respectively. The first gate structure extends through an upper portion of the first active pattern. The second gate structure is on an upper surface and an upper sidewall of the second active pattern. The source/drain layer is on a portion of the second active pattern that is adjacent to the second gate structure. The bit line structure is on a central portion of the first active pattern, and overlaps the second gate structure in a horizontal direction. The contact plug structure is on opposing end portions of the first active pattern. The capacitor is on the contact plug structure.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    10.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20230389289A1

    公开(公告)日：2023-11-30

    申请号：US18171171

    申请日：2023-02-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SEOKHAN PARK ,  KISEOK LEE ,  SEOKHO SHIN ,  HYUNGEUN CHOI ,  BOWON YOO

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/05

    Abstract: A semiconductor device includes bit line structures on a substrate. Each bit line structure extends in a second direction, and the bit line structures are spaced apart from each other in a first direction. The semiconductor device further includes semiconductor patterns spaced apart from each other in the second direction on each of the bit line structures, insulating interlayer patterns between neighboring ones of the semiconductor patterns in the first direction, and word lines spaced apart from each other in the second direction on the bit line structures. Each word line extends in the first direction adjacent to the semiconductor patterns. The semiconductor device further includes capacitors disposed on and electrically connected to the semiconductor patterns, respectively. A seam extending in the second direction is formed in each of the insulating interlayer patterns.

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