公开(公告)号：JP2000350166A

公开(公告)日：2000-12-15

申请号：JP15472099

申请日：1999-06-02

Applicant: SONY CORP

Inventor： YOSHIHIRO TOSHITAKA

IPC: H04N5/95

Abstract: PROBLEM TO BE SOLVED: To provide a PLL that can reduce a lock time in transition while keeping stability in a steady-state. SOLUTION: This PLL is provided with an error calculation section 40 that calculates a phase difference correction value based on initial phase difference data and provides an output of the value. The PLL outputs an internal frame reference signal based on the phase difference correction value outputted from the error calculation section. The error calculation section is provided with an integration term calculation system 20 that outputs integration term data, a proportional term calculation system 22 that outputs proportional term data, a differential calculation system 42 that outputs difference data between a frequency of a synchronizing reference signal and a reference frequency of a TV a signal, changeover switches 44, 46 that select the integration term calculation system 20 or the differential calculation system 42, and an adder 24 that sums the integration term data outputted from the integration term calculation system 20 and the proportional term data in response to the changeover of the switches or sums the differential data and the proportional term data to provide an output of the phase difference correction value. The high-speed lock performance in the case of transition and the stability in the steady state are made compatible by selecting the integration term calculation system 20 or the differential calculation system 42 by the switches in response to the magnitude correlation of the phase difference.

公开(公告)号：JPH11355713A

公开(公告)日：1999-12-24

申请号：JP16323198

申请日：1998-06-11

Applicant: SONY CORP

Inventor： TSUJIMURA TAKASHI ,  YOSHIHIRO TOSHITAKA

IPC: G06F13/38 ,  H04N5/262 ,  H04N5/91 ,  H04N9/80

Abstract: PROBLEM TO BE SOLVED: To record video data of pluralities of systems. SOLUTION: An extract section 25 extracts a flag to identify the NTSC or PAL system of a CIP(common isochronous packet) header and frame pulse data from a packet. A synchronization control section 22 sets a system (NTSC or PAL) of a signal to be outputted, confirms an identification flag of a system fed from the extract section 25 to control a software PLL processing section 21 and a data processing section 24. The software PLL processing section 21 generates a frame pulse synchronizing with frame pulse data supplied from the extract section 25. A frame pulse count processing section 23 discriminates whether or not the frame pulse from the software PLL processing section 21 corresponds to the setting by a synchronization control section 22 and sets a count of the counter. A data processing section 24 instructs a recording reproducing section 19 to record or stop data depending on the count.

公开(公告)号：JPH0668611A

公开(公告)日：1994-03-11

申请号：JP10642393

申请日：1993-05-07

Applicant: SONY CORP

Inventor： ISHIDA TAKEHITO ,  INOUE HAJIME ,  OKAMOTO ICHIRO ,  YOSHIHIRO TOSHITAKA

IPC: G11B20/18

Abstract: PURPOSE:To suppress the generation of noise due to an overwrite even in the case an error correction code is used. CONSTITUTION:A block is constituted of digital data and an error correcting parity, and a prescribed adding value is added to the parity at every record starting (overwriting) and the added value is recorded on a magnetic tape 12. At the time of reproduction, the value added to the parity is read by an OWP processing circuit 25, then a flag is generated when the added value is changed. Even in the data whose error is corrected by an error processing circuit 27 when the flag is inputted, they are interpolated from other data by an interpolation circuit 35.

公开(公告)号：JPH0564140A

公开(公告)日：1993-03-12

申请号：JP24274591

申请日：1991-08-28

Applicant: SONY CORP

Inventor： YOSHIHIRO TOSHITAKA

IPC: H04N5/783 ,  H04N5/92

Abstract: PURPOSE:To realize slow reverse reproduced video image by allowing a drive control means to control a tape drive means to implement usual drive and reversing for each prescribed time in the reverse slow reproduction mode and allowing a control means to apply write and read control to only recording data reproduced in the normal drive thereby implementing de-shuffling similarly to the normal state. CONSTITUTION:In the case of the slow reverse reproduction mode, two segments are at first reproduced normally and then 4 segments are rewound. Then 2 segments are reproduced normally again and a timing control circuit 26 is used to store data once in a memory in a reproduction digital data processing circuit 15 and to read the data.

公开(公告)号：JP2003169285A

公开(公告)日：2003-06-13

申请号：JP2001369103

申请日：2001-12-03

Applicant: SONY CORP

Inventor： YOSHIDA YONAKO ,  YOSHIHIRO TOSHITAKA

IPC: H04N5/783 ,  G11B20/10 ,  H04N5/76 ,  H04N5/92

Abstract: PROBLEM TO BE SOLVED: To provide an image reproducing device that can stabilize image reproduction at variable speed reproduction, simplify the configuration required for the processing, reduce the cost and enhance the processing speed. SOLUTION: A latch data generating section 62 supplies a SYNC/ID detection request data to a SYNC/ID detection section 22. The SYNC/ID detection section 22 detects data on the basis of the SYNC/ID request data and supplies the data to a latch data generating section 62 as the SYNC/ID detection data. The latch data generating section 62 generates latch data on the basis of the SYNC/ID detection data and supplies the latch data to a capstan servo arithmetic section 71. The capstan servo arithmetic section 71 carries out capstan servo arithmetic processing on the basis of the latch data and supplies the result to a PWM generating section 64. The PWM generating section 64 supplies a PWM signal to a driver 32 according to an arithmetic result to control a capstan motor 34. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002313033A

公开(公告)日：2002-10-25

申请号：JP2001113987

申请日：2001-04-12

Applicant: SONY CORP

Inventor： YOSHIHIRO TOSHITAKA ,  ABE FUMIYOSHI

IPC: G11B7/00 ,  G11B20/10 ,  G11B20/12 ,  G11B27/00 ,  G11B27/10 ,  G11B27/30 ,  H03M13/29 ,  H04N5/7826 ,  H04N5/783 ,  H04N5/92 ,  H04N5/93 ,  H04N5/937 ,  H04N9/82

Abstract: PROBLEM TO BE SOLVED: To ensure playbacks in variable speeds in a long-time mode. SOLUTION: When image data for playbacks in variable speeds (for example, 16-times speed playback) are dispersedly recorded on positions where a rotary head traces during playbacks in variable speeds, the number of recording times of the same image data for playbacks in variable speeds is increased and the number of sink blocks to be recorded at once is reduced in a long-time mode compared to the case of standard mode recording. For example, in the standard mode, six sink blocks are recorded 3 times, and in the long-time mode, four sink blocks are recorded 4 times.

公开(公告)号：JP2001352509A

公开(公告)日：2001-12-21

申请号：JP2000171576

申请日：2000-06-08

Applicant: SONY CORP

Inventor： YOSHIHIRO TOSHITAKA

IPC: H04N5/783 ,  G11B15/14 ,  G11B15/467 ,  H04N5/92

Abstract: PROBLEM TO BE SOLVED: To provide an image reproducing device that can stably reproduce an image signal recorded on a recording tape medium even at a variable speed reproduction. SOLUTION: A capstan servo-arithmetic section 71 obtains a speed error from time data C received from a time detection section 65 based on a capstan motor rotation detection pulse. Furthermore, the capstan servo arithmetic section 71 obtains an SB phase error based on an SB No. and Tr No. and an SB phase error detected by a SYNC/ID detection section 22. Furthermore, the capstan servo-arithmetic section 71 obtains a time phase error from time data B outputted from a time detection section 62 based on time data A received from the time detection section 62 depending on the RF position detection pulse outputted from an RF signal position detection section 30 and time data B outputted from the time detection section 62. The capstan servo-arithmetic section 71 outputs a signal to control the capstan motor to a PWM generating section 63 depending on the error above.

公开(公告)号：JP2001298706A

公开(公告)日：2001-10-26

申请号：JP2000115070

申请日：2000-04-17

Applicant: SONY CORP

Inventor： ENOMOTO TAKURO ,  YOSHIHIRO TOSHITAKA ,  YAMAMURA TAKAYA ,  HAYAKAWA TOMOO

IPC: H04N5/783 ,  G11B20/10 ,  H04N5/92 ,  H04N19/103 ,  H04N19/134 ,  H04N19/176 ,  H04N19/46 ,  H04N19/60 ,  H04N19/625 ,  H04N19/70 ,  H04N7/30

Abstract: PROBLEM TO BE SOLVED: To easily fix a code quantity for data for special reproduction, SOLUTION: A compression section 1 compresses video data in compliance with the MPEG system. An I picture separation section 2 separates an I picture from the compressed video data. A special reproduction data generating section 3 extracts a DC component from a DCT coefficient of the I picture separated by the I picture separation section 2 and supplies the DC component to a data length adjustment section 4 as special reproduction data. The data length adjustment section 4 adjusts (limits) the length of the data from the special reproduction data generating section 3 and supplies the length of the data to a multiplexer section 5. The multiplexer section 5 multiplexes the video data from the compression section 1, the data from the data length adjustment section 4, compressed audio data separately supplied and prescribed system data. A recording format processing section 6 adds an error correction code to the multiplexed data from the multiplexer section 5, applies modulation processing to the multiplexed data and supplies the result to a rotary head (not shown), which records the resulting data to a magnetic tape 7.

公开(公告)号：JPH09231680A

公开(公告)日：1997-09-05

申请号：JP6522796

申请日：1996-02-26

Applicant: SONY CORP

Inventor： OTA HIROSHI ,  YOSHIHIRO TOSHITAKA

IPC: H04N5/765 ,  G11B15/02 ,  G11B20/00 ,  G11B20/10

Abstract: PROBLEM TO BE SOLVED: To prevent the occurrence of oscillation even at the time of connecting digital interface input/output terminals and line input/output terminals of two digital video tape recorders respectively to each other. SOLUTION: Dubbing is performed by recording with the 1st digital video tape recorder 20 and reproducing with the 2nd digital video tape recorder 30. The digital interface input/output terminals are connected to each other, while the line output terminal 22 of the 1st digital video tape recorder 20 is connected with the line input terminal 31 of the 2nd digital video tape recorder 30. In the 2nd digital video tape recorder 30, the line input terminal 31 is set to be active, and when the inside operating state becomes a stop mode, the digital interface input/output terminal 33 is set to the output inhibit state by cooperation of a mode control part and a digital interface input/output control part of the 2nd digital video tape recorder 30 to cut off a signal loop to prevent the oscillation.

公开(公告)号：JPH0541873A

公开(公告)日：1993-02-19

申请号：JP21780991

申请日：1991-08-03

Applicant: SONY CORP

Inventor： YOSHIHIRO TOSHITAKA

IPC: H04N5/91 ,  H04N9/79

Abstract: PURPOSE:To improve the color reproducibility and to prevent blur of color or the like by sampling an input video signal while deviating its sampling phase by 2pi/n. CONSTITUTION:The device is provided with a 1st changeover switch 3 selecting any of a sampling clock of a chroma signal fed from a 1st clock generating circuit 5 and a sampling clock of a clock signal whose phase is deviated by 2pi/n fed from a half synchronization phase shift circuit 4 for each frame in response to an output from an AND gate 2. The sampling means of the recording system samples the input video signal for each frame while deviating the sampling phase by 2pi/n and records the result onto a recording medium and the reproduction system samples the reproduction video signal obtained by reproducing the video signal recorded on the recording medium for each frame while deviating the sampling phase by 2pi/n to form one still picture signal with data by n-frames.