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    11.
    发明专利
    未知

    公开(公告)号：DE60322540D1

    公开(公告)日：2008-09-11

    申请号：DE60322540

    申请日：2003-10-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  NOTARANGELO GIUSEPPE ,  VISALLI GIUSEPPE

    IPC: H04L25/49 ,  H04B10/50 ,  H04B10/516 ,  H04B10/80

    Abstract: In a method for transmitting on an optical connection (16) a sequence of input data (b(t)) comprising first ("1") and second ("0") logic states, there is envisaged the operation of providing an optical source (15) for generating an optical signal to be transmitted on said optical connection (16), said optical source (15) being able to generate optical pulses at the occurrence of said first ("1") logic states. The method comprises the operation of: - encoding (470,570) said sequence of input data (b(t)) in an encoded sequence of data (B(t)) prior to transmission on said optical connection (16), where said encoding operation minimizes the first logic states ("1") in said encoded sequence of data (B(t)). A preferential application is to optical-fibre communication systems with on-chip integrated buses.

    12.
    发明专利
    未知

    公开(公告)号：DE60306895D1

    公开(公告)日：2006-08-31

    申请号：DE60306895

    申请日：2003-05-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  VISALLI GIUSEPPE

    IPC: H04B10/524 ,  H04L25/49

    Abstract: A data stream (b(t)) including high ("1") and low ("0") logical states is transmitted over an optical link (16) by means of an optical source (15) adapted to be driven (14) via said the data stream to generate an optical signal for transmission over the optical link (16). The optical signal includes optical pulses generated at the occurrence of high logical ("1") states in said data stream (b(t)). The input data stream (b(t)) is coded (2000) into a coded data stream (B(t)) prior to the transmission over the optical link (16). The coding step minimises the logical high states ("1") in the coded data stream (B(t)), and the optical source (15) is driven by means of the coded data stream (B(t)) wherein the number of logical high states ("1") has been minimised.

    15.
    发明专利
    未知

    公开(公告)号：DE60233056D1

    公开(公告)日：2009-09-03

    申请号：DE60233056

    申请日：2002-10-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  AVELLONE GIUSEPPE ,  SALURSO ELENA ,  GALLUZZO AGOSTINO

    IPC: H04B1/707

    Abstract: To obtain frame synchronization and identify the cell codegroup in a cellular communication system (such as a system based upon the standard 3GPP FDD), there are available the synchronization codes (SSCH) organized in chips or letters transmitted at the beginning of respective slots. Slot synchronization is obtained previously in a first step of the operation of cell search. During a second step, there are acquired, by means of correlation (10) or fast Hadamard transform, the energy values corresponding to the respective individual letters with reference to the possible starting positions of the corresponding frame within the respective slot. Operating in a serial way (24) at the end of acquisition of the aforesaid energy values of the individual letters, or else operating in parallel, the energies of the corresponding words are determined. Of these eneriges only the maximum word-energy value and the information for the corresponding starting position are stored in a memory structure (22). Said maximum value and said starting position identify, respectively, the cell codes and the frame synchronization sought. A preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95, or WBCDMA.

    16.
    发明专利
    未知

    公开(公告)号：DE60209690D1

    公开(公告)日：2006-05-04

    申请号：DE60209690

    申请日：2002-09-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  NOTARANGELO GIUSEPPE

    IPC: G06F13/42 ,  G06F13/40

    Abstract: The process involves verifying recurrence of condition in which transmission on bus in non-encoded and encoded formats gives an identical switching activity on the bus for digital signals at a given instant. The transmission causes the additional signal associated with the signal to be transmitted at another instant to keep its logic value with respect to logic value assumed by additional signal for preceding instant. Independent claims are also included for the following: (1) an encoder for transmitting digital signals at given instants on a bus (2) a decoder for receiving digital signals transmitted on a bus (3) a computer program product directly loadable into memory of a computer and comprising a software code portions for implementing digital signal transmitting process.

    17.
    发明专利
    未知

    公开(公告)号：IT1310756B1

    公开(公告)日：2002-02-22

    申请号：ITTO991056

    申请日：1999-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  GIACALONE BIAGIO ,  MAMMOLITI FRANCESCO ,  GANGI EDMONDO

    IPC: G06F7/544 ,  G06F15/18 ,  G06G7/00 ,  G06N5/04 ,  H03K20060101

    Abstract: The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.

    18.
    发明专利
    未知

    公开(公告)号：ITTO991056D0

    公开(公告)日：1999-11-30

    申请号：ITTO991056

    申请日：1999-11-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAPPALARDO FRANCESCO ,  GIACALONE BIAGIO ,  MAMMOLITI FRANCESCO ,  GANGI EDMONDO

    IPC: G06F7/544 ,  G06F15/18 ,  G06G7/00 ,  G06N5/04 ,  H03K20060101

    Abstract: The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.

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